A 300-GHz-Band 36-Gb/s Scalable 2-D Phased-Array CMOS Double Superheterodyne Receiver

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Abstract
This paper presents a near-λ/2-antenna-pitch 2D phased-array CMOS receiver to address the challenge of implementing sub-THz beamforming with the narrow λ/2 (555 μ m at 270 GHz) antenna pitch. A double superheterodyne architecture is adopted to reduce the area occupied by the 2D RX array circuits by locating the E-and H-plane phase control circuits outside the array. Additionally, interpolated feeding is employed to enlarge the area available for the RX circuits by enabling an n-byn array of RX elements to feed a near-λ/2-pitch (2n -1)-by-(2n -1) antenna array composed of main and auxiliary antennas. A 40-nm CMOS prototype with 2×2 RX elements feeding 3×3 antenna elements demonstrate beam scanning ranges of approximately ±20∘ and ±30∘ in the E-and Hplanes, respectively, and achieves 36 Gb/s QPSK signal transmission over a distance of 5 cm.
Funding Information
  • Ministry of Internal Affairs and Communications of Japan (JPJ000254)