Shinsuke Hara

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

Increasing datacenter demands require power-efficient optical interconnects. However, a conventional standard transmitter using a silicon rib-waveguide Mach-Zehnder modulator and voltage-mode driver has low efficiency and consumes watt-class high power and occupies a several-square-millimeter footprint, which limits large-scale integration for parallel transmission. This paper presents a transmitter consisting of a compact photonic crystal waveguide (PCW) modulator and a current-mode open-collector driver. The PCW modulator is designed to have high impedance in addition to the slow-light effect. The driver connected to the modulator without termination resistors is optimized based on electronics-photonics co-simulations using a standard electronic circuit simulator with an in-house photonic model library. Co-packaging these dramatically reduces the power consumption to 50 mW and a bit energy to 0.78 pJ/bit at 64-Gbaud, and the footprint to 0.66 mm². This result represents a significant advancement toward the integration of a large number of transmission channels with no temperature control.

Sub-terahertz (Sub-THz) communication systems are a promising technology for next-generation high-speed, high-capacity wireless networks. Achieving this requires highly integrated antenna-in-package (AiP) solutions combining antennas and radio frequency integrated circuits (RFICs). However, high-frequency operation and dense integration increase RFIC heat density, potentially degrading AiP performance and reliability. This article proposes a sub-THz AiP with both excellent RF and thermal performance. The design features a multilayer antenna structure on a low-loss dielectric substrate, minimizing RFIC-to-antenna connections and radiating toward the substrate edge. A dual-sided heat dissipation structure is also introduced for efficient thermal management in stacked configurations. Validation through simulations and measurements confirmed good reflection characteristics ( $\vert $ S $11\vert \lt $ –10 dB), 15 dBi gain, and thermal resistance below 4.1 K/W. 2-D beam steering was also demonstrated, highlighting the effectiveness of the proposed co-design approach.

To realize the practical application of sub-THz band wireless communication toward 6G, it is necessary to develop AiP modules with compact size and low cost. This letter discusses the design of a miniaturized AiP module for high-speed wireless communication targeting extended reality (XR) applications in medical operating rooms as an example of 6G use cases. By integrating waveguide antenna array along with a compact divider/combiner within the multilayer substrates, the module achieves a small form factor of $8.42\times 20.0\times 1.37$ mm while integrating radio frequency integrated circuit (RFIC) and peripheral surface mount components. The measurement shows a data rate of 40 Gb/s at a 3 m distance in the 150 GHz band with an excellent transmission energy efficiency of 35.7 pJ/bit.

This paper presents a near-λ/2-antenna-pitch 2D phased-array CMOS receiver to address the challenge of implementing sub-THz beamforming with the narrow λ/2 (555 μ m at 270 GHz) antenna pitch. A double superheterodyne architecture is adopted to reduce the area occupied by the 2D RX array circuits by locating the E-and H-plane phase control circuits outside the array. Additionally, interpolated feeding is employed to enlarge the area available for the RX circuits by enabling an n-byn array of RX elements to feed a near-λ/2-pitch (2n -1)-by-(2n -1) antenna array composed of main and auxiliary antennas. A 40-nm CMOS prototype with 2×2 RX elements feeding 3×3 antenna elements demonstrate beam scanning ranges of approximately ±20∘ and ±30∘ in the E-and Hplanes, respectively, and achieves 36 Gb/s QPSK signal transmission over a distance of 5 cm.

A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

This work presents a D-band (110–170 GHz) CMOS transceiver (TRX) chipset that covers a 56-GHz (114–170 GHz) signal-chain bandwidth. Both the transmitter (TX) and the receiver (RX) operate as heterodyne architectures with external intermediate frequency (IF) and local oscillator (LO) signals. An eight-way low- Q power-combined power amplifier (PA), a two-way low- Q power-combined low-noise amplifier (LNA), wideband-impedance-transformation passive mixers, common-source-based cascaded distributed amplifiers (DAs), and a low-loss wideband chip-to-waveguide printed circuit board (PCB) transition are proposed with improved bandwidth and linearity to support high-order wideband quadrature amplitude modulation (QAM) signals. The TRX chipset was fabricated using a 65-nm CMOS process. The TX achieves a 13-dBm saturated output power at 130 GHz with 1150-mW dc power. The RX achieves a 12-dB noise figure (NF) with 550-mW dc power. The proposed TRX chipset achieves a data rate of 200 Gb/s by 32QAM in the single-input–single-output (SISO) over-the-air (OTA) measurement at 0.32 m. A data rate of 150 Gb/s by 16QAM is realized with 43-dBi antennas at 15 m. Additionally, a 640-Gb/s 4 $\times$ 4 OTA line-of-sight multiinput multioutput (LOS-MIMO) is demonstrated at 0.52 m.

This paper presents a low-imbalance and inductor-less active balun. The large immittance of the parasitics increases gain and phase errors in single-ended-to-differential conversion at high frequencies. Positive feedback is effective in reducing these errors. However, there is a trade-off between the stability of the feedback and the imbalance correction. This paper analyzes this trade-off, and the common-mode rejection ratio (CMRR) was improved by adding a capacitor. Besides, we established the feedback loops for the imbalance correction are also available for bandwidth extension, that is the additional capacitor improves not only the CMRR but also the high-frequency gain. This peaking technique removes inductors that consume large chip areas. The balun was fabricated in a 0.18- $\mu \text{m}$ CMOS process and achieved a small core area of 0.0058 mm2. In addition, a self-bias scheme using a current mirror was devised. It ensures a good bias current balance and reduces errors. The manufacturing variation of the fabricated baluns was statistically evaluated. To obtain the 99.7% limit of the CMRR, we extended the theory of the random CMRR to the complex plane. The measurement results demonstrated small errors within −0.1±0.2 dB and −0.18±1.17° including a variation of $\pm 3\sigma $ from DC to 8.0 GHz.

Photonic computing has been intensively studied to explore the ultrahigh bandwidth of lightwaves. However, electronic support is indispensable for the post-processing and control of photonic systems owing to the difficulties encountered in all-optical processing. Herein, we demonstrate an ultrafast silicon circuitry capable of conducting thresholding operations on incoming chaotically oscillating high-bandwidth signals. Such circuits are critical elements in ultrafast random-number generators and photonic reinforcement learning that exploit chaotically oscillating time series. The circuit design, including active inductors for bandwidth expansion, and proof-of-principle fabricated device operations are demonstrated using a 180 nm silicon complementary metal–oxide–semiconductor technology node.

A novel × 6 frequency multiplier chain with center frequency of 260 GHz is developed in 40 nm CMOS and measured through this work. The multiplication is accomplished through an x3 frequency multiplier followed by a doubler successive stage. A 4-way signal combiner is employed to enhance the output power, whereas phase shifters are dedicated for compensating the possible phase deviations between the different combined ways, and consequently maintain the combining efficiency. For further output power boosting, the output matching network of 260 GHz frequency doubler is optimized, and a stacked amplifier with 11.5 dBm is employed as a driving amplifier. The multiplier has been fabricated and a peak output power of 3.0 dBm is measured at 260 GHz with a 3-dB bandwidth of 17 GHz.