Akifumi Kasamatsu

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

To realize the practical application of sub-THz band wireless communication toward 6G, it is necessary to develop AiP modules with compact size and low cost. This letter discusses the design of a miniaturized AiP module for high-speed wireless communication targeting extended reality (XR) applications in medical operating rooms as an example of 6G use cases. By integrating waveguide antenna array along with a compact divider/combiner within the multilayer substrates, the module achieves a small form factor of $8.42\times 20.0\times 1.37$ mm while integrating radio frequency integrated circuit (RFIC) and peripheral surface mount components. The measurement shows a data rate of 40 Gb/s at a 3 m distance in the 150 GHz band with an excellent transmission energy efficiency of 35.7 pJ/bit.

This paper presents a near-λ/2-antenna-pitch 2D phased-array CMOS receiver to address the challenge of implementing sub-THz beamforming with the narrow λ/2 (555 μ m at 270 GHz) antenna pitch. A double superheterodyne architecture is adopted to reduce the area occupied by the 2D RX array circuits by locating the E-and H-plane phase control circuits outside the array. Additionally, interpolated feeding is employed to enlarge the area available for the RX circuits by enabling an n-byn array of RX elements to feed a near-λ/2-pitch (2n -1)-by-(2n -1) antenna array composed of main and auxiliary antennas. A 40-nm CMOS prototype with 2×2 RX elements feeding 3×3 antenna elements demonstrate beam scanning ranges of approximately ±20∘ and ±30∘ in the E-and Hplanes, respectively, and achieves 36 Gb/s QPSK signal transmission over a distance of 5 cm.

A D-band (114--170GHz) CMOS transceiver (TRX) chipset covering a 56GHz signal-chain bandwidth with a 640-Gb/s data rate is proposed in this work. The design includes an 8-way low-Q power-combined power amplifier (PA), a 2-way low-Q power-combined low noise amplifier (LNA), wideband-impedance-transformation mixers, and common-source-based cascaded distributed amplifiers (DA) to improve bandwidth and linearity. The proposed TRX chipset achieves a 200Gb/s SISO data rate and a 640Gb/s MIMO data rate.

This work presents a D-band (110–170 GHz) CMOS transceiver (TRX) chipset that covers a 56-GHz (114–170 GHz) signal-chain bandwidth. Both the transmitter (TX) and the receiver (RX) operate as heterodyne architectures with external intermediate frequency (IF) and local oscillator (LO) signals. An eight-way low- Q power-combined power amplifier (PA), a two-way low- Q power-combined low-noise amplifier (LNA), wideband-impedance-transformation passive mixers, common-source-based cascaded distributed amplifiers (DAs), and a low-loss wideband chip-to-waveguide printed circuit board (PCB) transition are proposed with improved bandwidth and linearity to support high-order wideband quadrature amplitude modulation (QAM) signals. The TRX chipset was fabricated using a 65-nm CMOS process. The TX achieves a 13-dBm saturated output power at 130 GHz with 1150-mW dc power. The RX achieves a 12-dB noise figure (NF) with 550-mW dc power. The proposed TRX chipset achieves a data rate of 200 Gb/s by 32QAM in the single-input–single-output (SISO) over-the-air (OTA) measurement at 0.32 m. A data rate of 150 Gb/s by 16QAM is realized with 43-dBi antennas at 15 m. Additionally, a 640-Gb/s 4 $\times$ 4 OTA line-of-sight multiinput multioutput (LOS-MIMO) is demonstrated at 0.52 m.

This paper presents the design and measurements of a 215-252GHz 40nm bulk CMOS frequency doubler with a 6.8dBm deliverable peak output power and a conversion gain of 11.8dB. The designed chip is composed of a 28.5dB gain 6-stages 110GHz power amplifier, an optimized push-push doubler biased in class-C configuration, and an output impedance matching network. A numerical method had been applied here for designing each implemented matching network achieving the optimum matching while maintaining the minimum insertion loss as well. The presented design shows the highest output power among the other sub-THz-designed CMOS counterparts. The design occupies an area of 0.795mm² and shows a total DC power dissipation of 262mW and DC-RF efficiency of 1.87.

Hole-tunneling Si0.82Ge0.18/Si asymmetric triple-barrier (TB) resonant tunneling diodes (p-RTDs) were created by sputter epitaxy instead of conventional chemical vapor phase epitaxy. As a result, a peak current density (PCD) of 297 kA/cm2 with a peak-to-valley current ratio of 7.3 was recorded at room temperature. The observed high planarity of the films grown by sputter epitaxy is also considered one of the factors behind the high PCD. From the results of self-consistent theoretical calculations of current–voltage characteristics using box-shaped potentials as a first approximation and considering space charge effects of quantum wells, heavy-hole-to-heavy-hole and light-hole-to-light-hole state transitions under the tunneling conditions of the TB potential structure applied in this study were found to be inherent current paths. Moreover, the light and heavy hole currents contribute almost equally to the overall device current, resulting in a theoretical PCD of 637 kA/cm2, which is close to the experimental result. Further analytical simulations with adjusted series resistance and thickness of the nondoped layer allowed the alignment of the theoretically obtained PCD voltage position with the experimentally obtained one. Thus, the theoretical and analytical calculations explain the operation mechanisms of SiGe/Si p-RTDs, and the proposed fabrication method using our sputter epitaxy method is very useful for the actual production of high-PCD SiGe/Si p-RTDs operating at room temperature.

Photonic computing has been intensively studied to explore the ultrahigh bandwidth of lightwaves. However, electronic support is indispensable for the post-processing and control of photonic systems owing to the difficulties encountered in all-optical processing. Herein, we demonstrate an ultrafast silicon circuitry capable of conducting thresholding operations on incoming chaotically oscillating high-bandwidth signals. Such circuits are critical elements in ultrafast random-number generators and photonic reinforcement learning that exploit chaotically oscillating time series. The circuit design, including active inductors for bandwidth expansion, and proof-of-principle fabricated device operations are demonstrated using a 180 nm silicon complementary metal–oxide–semiconductor technology node.

A novel × 6 frequency multiplier chain with center frequency of 260 GHz is developed in 40 nm CMOS and measured through this work. The multiplication is accomplished through an x3 frequency multiplier followed by a doubler successive stage. A 4-way signal combiner is employed to enhance the output power, whereas phase shifters are dedicated for compensating the possible phase deviations between the different combined ways, and consequently maintain the combining efficiency. For further output power boosting, the output matching network of 260 GHz frequency doubler is optimized, and a stacked amplifier with 11.5 dBm is employed as a driving amplifier. The multiplier has been fabricated and a peak output power of 3.0 dBm is measured at 260 GHz with a 3-dB bandwidth of 17 GHz.

A 76-Gbit/s 265-GHz CMOS receiver (RX) modularized with a WR-3.4 waveguide interface is presented. It is a mixer-first RX fabricated using a 40-nm CMOS technology. The primary design focus is simplicity and the resulting low noise and loss and high conversion gain (CG). To allow for both on-wafer and packaged measurements, ON-chip transmission lines are designed such that their characteristics are relatively insensitive to the presence or absence of adhesive covering the chip. The RX chip is flip-chip-mounted on a multilayer printed circuit board (PCB). Built into the PCB is a waveguide transition using double-resonant stacked patches for wideband operation. The CMOS RX module achieves the highest wireless data rate of 76 Gbit/s with 16 QAM, which is comparable to 80 Gbit/s reported previously for a CMOS RX with on-wafer probing measurement.