Reference Spur Reduction Techniques for a Phase-Locked Loop

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Abstract
This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead. This leakage compensation loop senses the leakage current of the loop filter from the up and down pulse widths in the steady state, and compensates for the charge loss due to the leakage current. A systematic approach for the reference spur reduction is also proposed. Since a PLL operates as a band pass filter in the frequency domain, the reference spur can be filtered out by cascading the PLLs. The optimization technique for the cascaded PLLs is presented that minimizes the reference spur without degrading the phase noise performance. The proposed techniques are verified using an 800-MHz PLL chip fabricated in 65-nm CMOS process. The prototype PLL achieves the reference spur of -68.57 dBc, while the conventional charge-pump PLL without the proposed spur reduction techniques achieves -42.83 dBc.
Funding Information
  • IC Design Education Center
  • Ministry of Trade, Industry and Energy
  • Korea Semiconductor Research Consortium (KSRC) Support Program for the Development of the Future Semiconductor Device
  • BK21 Program, South Korea

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