Deog-Kyoon Jeong

As the demand for high-speed memory interfaces continues to grow, the need for effective testing methodologies becomes increasingly critical. Traditional automatic test equipment (ATE) systems are limited in their capability to test advanced signaling methods such as pulse amplitude modulation-4 (PAM-4) due to their reliance on non-return-to-zero (NRZ) signaling. This article presents a PAM-4 transceiver designed to bridge the gap between the tester and the memory, boosting the PAM-4 testing data rate up to 48 Gb/s using existing NRZ-based ATE. The proposed work provides enhanced transition slope and ratio level mismatch (RLM) control through precise gate voltage adjustment, resulting in improved test accuracy. The prototype was fabricated in 40-nm CMOS technology and occupies an active area of 2.34 mm². The proposed work operates at 48 Gb/s/pin, demonstrating an energy efficiency of 1.85 pJ/bit in write mode and 2.97 pJ/bit in read mode for the PAM-4 test, respectively.

This article proposes a deadzone-free clock and data recovery (CDR) without an external reference clock. To extract a frequency difference, the proposed referenceless CDR adopts a stochastic frequency detector, which utilizes consecutive data and edge samples. Although the probability-based frequency detection (FD) technique is promising, a deadzone should be carefully considered to prevent false locking. Therefore, by analyzing the stochastic FD thoroughly, this work proposes an autocovariance-based stochastic FD (ASFD) to resolve the deadzone issue and provide a more robust CDR operation. Since the autocovariance function is easily implemented in the digital domain, the proposed digital CDR with the ASFD improves the frequency tracking ability with minimal hardware overhead. Fabricated in 40-nm CMOS technology, the prototype CDR occupies an active area of 0.032mm². The CDR achieves a seamless frequency locking with a capture range from 14 to 32 Gb/s and frequency acquisition time within $7~{\mu }$ s. At 32 Gb/s, the CDR achieves a bit error rate (BER) of less than $10{^{-12}}$ and an energy efficiency of 1.15 pJ/b at a supply voltage of 1.0 V.

This brief proposes a digital phase-locked loop (DPLL) with a power supply noise (PSN) regulated ring-type digitally controlled oscillator (DCO) using an nMOS shunt regulator array. The proposed nMOS array dynamically detects the PSN and creates a pathway, channeling the PSN forwarded through the digitally controlled resistor (DCR) directly to the ground. To support the proposed power supply noise compensation (PNC) technique in wide-range operation, the output bits from the digital loop filter (DLF) control not only the DCR but also the total transconductance of the nMOS array. The supply-sensing amplifier (SSA) between the supply and the gates of the nMOS array amplifies supply noise to lower the voltage headroom, allowing the DCO to run faster. Fabricated in 40-nm CMOS technology, the prototype DPLL demonstrates an rms jitter of 1.27 ps under 1 MHz, 20-mV_PP sinusoidal noise, while the rms jitter without the regulator is measured as 3.26 ps. The total power consumption and area occupation of the DPLL are 13.5 mW and 0.066 mm², respectively. The proposed scheme for PNC contributes only 1.90 mW and 0.0017 mm², representing 14.1% and 2.8% of the total, respectively.

A change from a non-return-to-zero (NRZ) signaling to a four-level pulse amplitude modulation (PAM-4) signaling causes various challenges in clock and data recovery (CDR) designs as well as analog-front-end (AFE) designs. A PAM-4 CDR with a 2x-oversampling phase detector (PD) has an issue of increased pattern-dependent jitter due to asymmetric transitions. This work investigates a similar problem in a baud-rate CDR by analyzing the PD characteristics. In the PAM-4 baud-rate sampling, the transitions are classified into two types: full-swing transitions and non-full-swing transitions. Since utilizing the non-full-swing transitions can affect the jitter tracking ability, careful consideration of decisions using these transitions is necessary to optimize the jitter performance. To address this issue, we propose an asymmetric-weighted PD that minimizes pattern-dependent jitter and maximizes a transition density by utilizing both the full-swing transitions and the non-full-swing transitions. Using a pseudo-linear analysis, the proposed PD achieves improved jitter performance compared to the conventional PD. Fabricated in 28-nm CMOS process, a prototype PAM-4 receiver with the proposed CDR is demonstrated at 40 Gb/s. The CDR achieves a bit error rate (BER) less than 10 $^{-9}$ and an energy efficiency of 1.65 pJ/b.

This paper presents a 50-Gb/s receiver (RX) with an adaptive phase-shifting (APS) phase detector (PD) for four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR). The APS PD adopts a $\beta $ detector to achieve a unique locking point that resolves the dead-zone problem caused by the combination of the conventional baud-rate PD and adaptive decision feedback equalizer (DFE). The APS CDR is configured with a sign-sign minimum mean squared error (SS-MMSE) PD and an addition of a digital coefficient which is adaptively controlled through the $\beta $ detector by detecting pre-cursor inter-symbol interference (ISI) dependency of 1-level transitions. Therefore, the proposed CDR does not rely on external coefficients. Furthermore, adaptive programmable gain amplifiers (PGAs) and DFE are implemented with the APS CDR to compensate the pre and post-cursor ISIs, and main-cursor level. Since the adaptive equalizers and the APS CDR share the error samplers, no additional analog hardware is required. Fabricated in 28-nm CMOS technology, a prototype PAM-4 RX operates at 50 Gb/s and occupies an active area of 0.16 mm $^{2}$ . The RX tested over a 25.3-dB loss channel achieves a bit error rate (BER) of less than 10 $^{-12}$ and energy efficiency of 2.52 pJ/b.

The first chip I designed during my master’s degree program at Seoul National University in 1985 was a dual-modulus prescaler used for frequency synthesis in a digitally tuned automotive radio receiver. Since the incoming frequency was high, being close to an FM carrier, the chip was made mostly of CMLs using hundreds of transistors with a bipolar process. This chip was fabricated and measured, but unfortunately, it did not work. It oscillated at around 5 MHz. A bandgap reference that uses feedback was employed to compensate for the temperature variation, but the required compensation capacitance was not accurately calculated, causing instability. At that time, since a circuit simulation tool was unavailable, I could not calculate the exact loop characteristics and ended up adding an insufficient amount of capacitance. Although succeeding in the revised chip by inserting a capacitor several times larger than the value estimated by hand calculation, I became acutely aware of the need for a circuit design tool. Today, more than 40 years later, it is an incredible honor to receive the IEEE Technical Field Award, commemorating Professor Donald O. Pederson, who pioneered Simulation Program With Integrated Circuit Emphasis, which has become a standard circuit simulation tool. I entered the doctoral program at the University of California, Berkeley (UC Berkeley), and was taught by great professors, and it is unfortunate that I said hello to Prof. Pederson only a few times in the hallway.

This article presents an external-clock-free fully synthesizable digital low-dropout regulator (DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based load-state decision is exploited to change an internal clock frequency depending on a load state, while employing a single comparator, a single reference voltage, and a single delay line. In addition, for small voltage droop and short settling time without an output-load capacitor, a asynchronous response to voltage droop and a fast-recovery technique are exploited using a load-direct droop detector and a coarse controller. Besides, in order to obtain full synthesizability, all circuits including pass gates are made up of industry-standard cells and all blocks are implemented using a commercial script-based auto place-and-route tool. The DLDO prototype fabricated in a 40-nm CMOS process occupies a total area of 0.0035 mm $^{2}$ . When load current is changed from 0.78 to 39.2 mA with 2.2-ns edge time, voltage droop and settling time are measured as 98 mV and 5 ns, respectively. Thanks to the full synthesizability and the output-capacitor-free design, 16.1-A/mm $^{2}$ current density is achieved, which is the best performance compared to prior state-of-the-art DLDOs.

This article presents the design of an area/ power-efficient discrete-time (DT) delta-sigma ( $\Delta\Sigma $ ) modulator suitable for multichannel sensor applications. First, the area efficiency of the modulator is achieved by optimizing the size of the sampling capacitor with the compact integrators based on the dynamic-boost inverter (DBI). The DBI is designed to have a small active area of only 0.00044 mm $^{{2}}$ , due to its self-bias scheme that eliminates the need for additional hardware for biasing circuitry. Second, the power efficiency is improved through the quantitative design approach to reduce the power consumption of the integrators by optimizing the gain–bandwidth product (GBW) of the DBI-based OTA in each integrator. In addition, the static current consumption of the integrators is further reduced due to the power-saving feature of the DBI utilizing the principle of a composite transistor. Finally, the self-bias scheme ensures that the DBI maintains a dc gain of 44.3 dB despite circuit mismatch by balancing the currents of the nMOS and pMOS transistors in the DBI. The prototype modulator, fabricated using 0.18- $\mu $ m CMOS technology, occupies an active area of 0.0939 mm $^{{2}}$ . For a 25-kHz bandwidth (BW), the modulator achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 84.0 dB, a peak SNR of 85.1 dB, and a DR of 87.1 dB with a power supply rejection ratio (PSRR) of 56.8 dB and a common-mode rejection ratio (CMRR) of 66.1 dB at a 1.8-V supply. The modulator also maintains an SNDR higher than 82.5 dB and a DR higher than 85.5 dB for a 5–25-kHz BW with an FoM $_{{W}}$ of 78.4–103.4 fJ/conversion at a 1.5–1.8-V supply.

This brief presents a 10 Gb/s receiver for an application processor (AP)-to-timing controller-embedded display (TED) interface that is capable of recovering its operating frequency fast from the sleep mode under the supply voltage drift. A hybrid clock and data recovery (CDR) loop is employed to support the fast entering and exiting of the sleep mode by adding AND gates to the digital loop filter, while offering good jitter performance by utilizing an analog loop filter. Also supply voltage drift cancellation (SVDC) circuit is added to maintain constant current in the presence of supply voltage drift. Thanks to the hybrid CDR and SVDC, even if the supply voltage drift occurs during the sleep mode, the same frequency is recovered fast without frequency re-tracking. A prototype chip fabricated in 28-nm CMOS technology occupies an active area of 0.089mm2 with 0.99-pJ/bit energy efficiency in the active mode. The measured results show that the frequency is recovered within 36 ns even if the worst-case supply voltage drift occurs during the sleep mode.

This brief presents a gradient-based maximum eye tracking (GMET) scheme employed in the forwarded-clock receiver, including baud-rate clock and data recovery (CDR) and 2-tap adaptive decision feedback equalization (DFE). By optimizing the widely used gradient ascent method for robust operation, GMET achieves low computational power and high stability. Also, simultaneous adaptation using the unified algorithm enables low power consumption and low design complexity. Compared with the previous baud-rate CDR, superior performance is demonstrated under high-loss conditions. The prototype receiver is fabricated in 28-nm CMOS and occupies an active area of 0.106 mm2. At the data rate of 28 Gb/s, the receiver consumes 47 mW, corresponding to an energy efficiency of 1.68 pJ/b. Furthermore, with a channel loss of 27.7 dB at the Nyquist frequency, joint operation of the CDR and the DFE adaptation offers measured results with a margin of 0.17 unit interval (UI) at a BER lower than 10-12.