Abstract
This work establishes a top-down design methodology for analog compute-in-memory (ACIM) systems that derives circuit-level noise bounds directly from application-specific accuracy constraints. Rather than relying on traditional bottom-up error simulation, we utilize a custom noise injection framework to extract layer-wise noise tolerance thresholds independent of the underlying hardware technology. These abstract thresholds are mathematically translated into minimum computational signal-to-noise ratio (compute SNR) requirements, forming a direct link between algorithm robustness and physical circuit limits. Hardware designers can utilize these SNR targets to reverse-engineer optimal design parameters, including bit precision, array sizing, and data converter scaling. Validated on the Mamba SSM architecture, our framework successfully isolates highly noise-tolerant operations from precision-critical layers, directly informing the design of energy-efficient ACIM systems tailored to specific machine learning workloads.
Funding Information
  • National Science Foundation (2023-JU-3133)
  • Defense Advanced Research Projects Agency (GR00024712)
  • National Science Foundation (DGE-2545526)

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