Laith A. Shamieh
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Laith A. Shamieh has a total of 10 co-authors. Here are the top co-authors by number of shared publications:
- Saibal Mukhopadhyay
Department of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA
2 shared publications - Wei-Chun Wang
Georgia Institute of Technology, Atlanta, GA, USA
2 shared publications - Amol Domaji Gaidhane
Arizona State University, Tempe, AZ, United States
1 shared publication - Arijit Raychowdhury
Georgia Institute of Technology
1 shared publication - Han Cho
Georgia Institute of Technology, Atlanta, GA, USA
1 shared publication - Isha Chakraborty
Georgia Institute of Technology, Atlanta, GA, USA
1 shared publication
Latest Publications
- Open Access
- 5 August 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
A Top-Down Design Methodology for Accuracy-to-Noise Mapping in Analog Compute-in-Memory Systems: Evaluation on Mamba
This work establishes a top-down design methodology for analog compute-in-memory (ACIM) systems that derives circuit-level noise bounds directly from application-specific accuracy constraints. Rather than relying on traditional bottom-up error simulation, we utilize a custom noise injection framework to extract layer-wise noise tolerance thresholds independent of the underlying hardware technology. These abstract thresholds are mathematically translated into minimum computational signal-to-noise ratio (compute SNR) requirements, forming a direct link between algorithm robustness and physical circuit limits. Hardware designers can utilize these SNR targets to reverse-engineer optimal design parameters, including bit precision, array sizing, and data converter scaling. Validated on the Mamba SSM architecture, our framework successfully isolates highly noise-tolerant operations from precision-critical layers, directly informing the design of energy-efficient ACIM systems tailored to specific machine learning workloads.
- 5 August 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessA Top-Down Design Methodology for Accuracy-to-Noise Mapping in Analog Compute-in-Memory Systems: Evaluation on Mamba
This work establishes a top-down design methodology for analog compute-in-memory (ACIM) systems that derives circuit-level noise bounds directly from application-specific accuracy constraints. Rather than relying on traditional bottom-up error simulation, we utilize a custom noise injection framework to extract layer-wise noise tolerance thresholds independent of the underlying hardware technology. These abstract thresholds are mathematically translated into minimum computational signal-to-noise ratio (compute SNR) requirements, forming a direct link between algorithm robustness and physical circuit limits. Hardware designers can utilize these SNR targets to reverse-engineer optimal design parameters, including bit precision, array sizing, and data converter scaling. Validated on the Mamba SSM architecture, our framework successfully isolates highly noise-tolerant operations from precision-critical layers, directly informing the design of energy-efficient ACIM systems tailored to specific machine learning workloads.
- Open Access
- 5 August 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-6
Cryogenic Operation of Computing-In-Memory based Spiking Neural Network
This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.
- 5 August 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-6
Open AccessCryogenic Operation of Computing-In-Memory based Spiking Neural Network
This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.