Cor Claeys
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Cor Claeys has a total of 146 co-authors. Here are the top co-authors by number of shared publications:
E. Simoen
34 shared publications- Eddy Simoen
Ghent University, Ghent, Belgium
4 shared publications P. Clauws
Department of Solid-state Science, Ghent University, B-9000 Gent, Belgium
4 shared publicationsA. Mercha
Imec, B-3001 Leuven, Belgium
3 shared publicationsA. Poyai
Imec, B-3001 Leuven, Belgium
3 shared publicationsEddy Simoen
IMEC, Leuven, Belgium
3 shared publications
Latest Publications
- 12 February 2015
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 62 (4) , 1079-1084
TCAD Strain Calibration Versus Nanobeam Diffraction of Source/Drain Stressors for Ge MOSFETs
TCAD finite-element process simulations have been performed on Ge-channel n and pMOSFETs with embedded source/drain stressors or a strained Ge channel on a relaxed SiGe strain relaxed buffer (SRB), respectively, and compared with nanobeam diffraction strain measurements. While there is overall a good agreement between the simulated and experimental strain profiles, some deviations may occur, due to the presence of extended defects in the strain relaxed Ge buffer layers. This highlights the importance of selection of a strain-free reference in the relaxed Ge or SiGe SRB.
- 12 February 2015
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 62 (4) , 1079-1084
TCAD Strain Calibration Versus Nanobeam Diffraction of Source/Drain Stressors for Ge MOSFETs
TCAD finite-element process simulations have been performed on Ge-channel n and pMOSFETs with embedded source/drain stressors or a strained Ge channel on a relaxed SiGe strain relaxed buffer (SRB), respectively, and compared with nanobeam diffraction strain measurements. While there is overall a good agreement between the simulated and experimental strain profiles, some deviations may occur, due to the presence of extended defects in the strain relaxed Ge buffer layers. This highlights the importance of selection of a strain-free reference in the relaxed Ge or SiGe SRB.
- 30 September 2011
- Published by Elsevier in Solid-State Electronics
- Vol. 63 (1) , 27-36
LKE and BGI Lorentzian noise in strained and non-strained tri-gate SOI FinFETs with HfSiON/SiO2 gate dielectric
- 30 September 2011
- Published by Elsevier in Solid-State Electronics
- Vol. 63 (1) , 27-36
LKE and BGI Lorentzian noise in strained and non-strained tri-gate SOI FinFETs with HfSiON/SiO2 gate dielectric
- 17 February 2010
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 31 (3) , 243-245
Influence of Fin Width on the Total Dose Behavior of p-Channel Bulk MuGFETs
A first assessment of the total dose behavior of bulk p-multiple-gate field-effect transistors (MuGFETs) is reported, and special attention is given to the effect of the fin width on the radiation behavior. It was found that the effect of radiation-induced traps in the shallow trench isolation is larger when the fin width decreases. This is in contrast to the total dose behavior of SOI MuGFETs.
- 17 February 2010
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 31 (3) , 243-245
Influence of Fin Width on the Total Dose Behavior of p-Channel Bulk MuGFETs
A first assessment of the total dose behavior of bulk p-multiple-gate field-effect transistors (MuGFETs) is reported, and special attention is given to the effect of the fin width on the radiation behavior. It was found that the effect of radiation-induced traps in the shallow trench isolation is larger when the fin width decreases. This is in contrast to the total dose behavior of SOI MuGFETs.
- 1 February 2010
- Published by Elsevier in Thin Solid Films
- Vol. 518 (9) , 2493-2496
Low-frequency noise assessment of the silicon passivation of Ge pMOSFETs
- 1 February 2010
- Published by Elsevier in Thin Solid Films
- Vol. 518 (9) , 2493-2496
Low-frequency noise assessment of the silicon passivation of Ge pMOSFETs
- 1 December 2009
- Published by Elsevier in Physica B: Condensed Matter
- Vol. 404 (23) , 4674-4677
Effects of irradiation induced lattice defects on standard trench and fine pattern trench IGBT characteristics
- 1 December 2009
- Published by Elsevier in Physica B: Condensed Matter
- Vol. 404 (23) , 4674-4677
Effects of irradiation induced lattice defects on standard trench and fine pattern trench IGBT characteristics
- 20 November 2009
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Device and Materials Reliability
- Vol. 10 (1) , 130-141
Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs
The electrostatic-discharge sensitivity of fully depleted SOI MOSFETs with ultrathin silicon body and ultrathin gate oxide is studied. An original and detailed electrical analysis is carried out in order to investigate the degradation of the electrical DC parameters and classify the observed failure modes and mechanisms. The impact of device geometry and strain engineering is also analyzed.
- 20 November 2009
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Device and Materials Reliability
- Vol. 10 (1) , 130-141
Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs
The electrostatic-discharge sensitivity of fully depleted SOI MOSFETs with ultrathin silicon body and ultrathin gate oxide is studied. An original and detailed electrical analysis is carried out in order to investigate the degradation of the electrical DC parameters and classify the observed failure modes and mechanisms. The impact of device geometry and strain engineering is also analyzed.
- 5 December 2008
- Published by Elsevier in Materials Science and Engineering: B
- Vol. 154-155, 49-55
Defect engineering aspects of advanced Ge process modules
- 5 December 2008
- Published by Elsevier in Materials Science and Engineering: B
- Vol. 154-155, 49-55
Defect engineering aspects of advanced Ge process modules
- 1 October 2008
- Published by Elsevier in Materials Science in Semiconductor Processing
- Vol. 11 (5-6) , 147
E-MRS 2008 Spring Conference Symposium J: Beyond Silicon Technology: Materials and Devices for Post-Si CMOS
- 1 October 2008
- Published by Elsevier in Materials Science in Semiconductor Processing
- Vol. 11 (5-6) , 147
E-MRS 2008 Spring Conference Symposium J: Beyond Silicon Technology: Materials and Devices for Post-Si CMOS
- 13 August 2008
- Published by IOP Publishing in Semiconductor Science and Technology
- Vol. 23 (9)
Modelling of threshold voltage and subthreshold slope of strained-Si MOSFETs including quantum effects
- 13 August 2008
- Published by IOP Publishing in Semiconductor Science and Technology
- Vol. 23 (9)
Modelling of threshold voltage and subthreshold slope of strained-Si MOSFETs including quantum effects
- 24 September 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 28 (10) , 919-921
On the Origin of the Excess Low-Frequency Noise in Graded-Channel Silicon-on-Insulator nMOSFETs
The origin of the low-frequency noise in graded- channel silicon-on-insulator nMOSFET is studied as a function of the back-gate bias at a low drain-to-source bias. It is shown that an excess noise peak that is correlated with the peak in the transconductance can be observed. This excess noise is due to a generation-recombination component in the low-frequency range, which is suppressed when the back gate is in accumulation mode.
- 24 September 2007
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 28 (10) , 919-921
On the Origin of the Excess Low-Frequency Noise in Graded-Channel Silicon-on-Insulator nMOSFETs
The origin of the low-frequency noise in graded- channel silicon-on-insulator nMOSFET is studied as a function of the back-gate bias at a low drain-to-source bias. It is shown that an excess noise peak that is correlated with the peak in the transconductance can be observed. This excess noise is due to a generation-recombination component in the low-frequency range, which is suppressed when the back gate is in accumulation mode.