Sergio Soto-Aguilar
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Sergio Soto-Aguilar has a total of 12 co-authors. Here are the top co-authors by number of shared publications:
- Edgar Sanchez-Sinencio
Department of Electrical and Computer Engineering, Texas AM University, College Station, TX, USA
4 shared publications Edgar Sanchez-Sinencio
Analog and Mixed-Signal Center, Texas A&M University, College Station, TX
2 shared publications- Johan Jair Estrada López
Faculty of Mathematics, Universidad Autónoma de Yucatán, Mérida 97000, Mexico
2 shared publications - Adriana Sanabria Borbon
Department of Electrical and Computer Engineering, Texas A&M University, College Station, Texas, USA
1 shared publication Adriana Sanabria-Borbon
Analog and Mixed-Signal Center, Texas A&M University, College Station, TX
1 shared publicationArunvenkatesh Alagappan
Analog and Mixed-Signal Center, Texas A&M University, College Station, USA
1 shared publication
Latest Publications
- Open Access
- 21 April 2021
- Published by MDPI AG in Electronics
- Vol. 10 (9) , 991
Design Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers
Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in in the multi-loop implementation with respect to the single-loop case.- 21 April 2021
- Published by MDPI AG in Electronics
- Vol. 10 (9) , 991
Open AccessDesign Trade-Offs in Common-Mode Feedback Implementations for Highly Linear Three-Stage Operational Transconductance Amplifiers
Fully differential amplifiers require the use of common-mode feedback (CMFB) circuits to properly set the amplifier’s operating point. Due to scaling trends in CMOS technology, modern amplifiers increasingly rely on cascading more than two stages to achieve sufficient gain. With multiple gain stages, different topologies for implementing CMFB are possible, whether using a single CMFB loop or multiple ones. However, the impact on performance of each CMFB approach has seldom been studied in the literature. The aim of this work is to guide the choice of the CMFB implementation topology evaluating performance in terms of stability, linearity, noise and common-mode rejection. We present a detailed theoretical analysis, comparing the relative performance of two CMFB configurations for 3-stage OTA topologies in an implementation-agnostic manner. Our analysis is then corroborated through a case study with full simulation results comparing the two topologies at the transistor level and confirming the theoretical intuition. An active-RC filter is used as an example of a high-linearity OTA application, highlighting a 6 dB improvement in in the multi-loop implementation with respect to the single-loop case. - Open Access
- 23 April 2020
- Published by MDPI AG in Electronics
- Vol. 9 (4) , 685
Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design
Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is to faster at evaluation compared with circuit simulations.- 23 April 2020
- Published by MDPI AG in Electronics
- Vol. 9 (4) , 685
Open AccessGaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design
Optimization algorithms have been successfully applied to the automatic design of analog integrated circuits. However, many of the existing solutions rely on expensive circuit simulations or use fully customized surrogate models for each particular circuit and technology. Therefore, the development of an easily adaptable low-cost and efficient tool that guarantees resiliency to variations of the resulting design, remains an open research area. In this work, we propose a computationally low-cost surrogate model for multi-objective optimization-based automated analog integrated circuit (IC) design. The surrogate has three main components: a set of Gaussian process regression models of the technology’s parameters, a physics-based model of the MOSFET device, and a set of equations of the performance metrics of the circuit under design. The surrogate model is inserted into two different state-of-the-art optimization algorithms to prove its flexibility. The efficacy of our surrogate is demonstrated through simulation validation across process corners in three different CMOS technologies, using three representative circuit building-blocks that are commonly encountered in mainstream analog/RF ICs. The proposed surrogate is to faster at evaluation compared with circuit simulations. - 1 August 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 566-569
Surrogate-based Optimization-aided Design for Low Power Analog Circuits
Automatic and flexible analog integrated circuit design is still an open topic. Simulation-based optimization is accurate but relies on the efficacy of heuristics to find a solution. Equation-based optimization is faster, can work with both gradients and heuristic algorithms but the accuracy depends on the set of equations. We propose an equation-based surrogate model that combines physics-based transistor model, curve fitting approximations for device parameters, and circuit analysis describing the metrics of the circuit to optimize. Two design examples are provided as proof of concept of the proposed optimization framework, a 2nd-order active-RC Butterworth filter, and a Capless-LDO. The results prove this technique to be effective finding solutions for different processes technologies and flexible to the specifications. Multi-objective optimization is used to generate a Pareto front representing the design trade-off.
- 1 August 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 566-569
Surrogate-based Optimization-aided Design for Low Power Analog Circuits
Automatic and flexible analog integrated circuit design is still an open topic. Simulation-based optimization is accurate but relies on the efficacy of heuristics to find a solution. Equation-based optimization is faster, can work with both gradients and heuristic algorithms but the accuracy depends on the set of equations. We propose an equation-based surrogate model that combines physics-based transistor model, curve fitting approximations for device parameters, and circuit analysis describing the metrics of the circuit to optimize. Two design examples are provided as proof of concept of the proposed optimization framework, a 2nd-order active-RC Butterworth filter, and a Capless-LDO. The results prove this technique to be effective finding solutions for different processes technologies and flexible to the specifications. Multi-objective optimization is used to generate a Pareto front representing the design trade-off.
- 19 February 2018
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 34 (3) , 313-320
A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits
- 19 February 2018
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 34 (3) , 313-320
A Time-Domain Digital-Intensive Built-In Tester for Analog Circuits
- 21 April 2016
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 88 (2) , 279-287
Clock harmonic distortion reduction technique for full tunable range in switched-R-MOSFET-C filters
- 21 April 2016
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 88 (2) , 279-287
Clock harmonic distortion reduction technique for full tunable range in switched-R-MOSFET-C filters
- 1 August 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15483746,p. 1037-1040
Reduced clock harmonic distortion technique in maximum tunable switched-R-MOSFET-C filters
In this paper a method to reduce the harmonic distortion caused by the switching operation in switched-R-MOSFET-C filters is presented. The technique is demonstrated through simulations and backed by analytical expressions for first order active RC and second order biquad filters; the improvement in clock distortion is presented and compared with previously reported architectures. The proposed harmonic cancellation technique shows an improvement of more than 33 dB over previous architectures without compromising the tuning range.
- 1 August 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 15483746,p. 1037-1040
Reduced clock harmonic distortion technique in maximum tunable switched-R-MOSFET-C filters
In this paper a method to reduce the harmonic distortion caused by the switching operation in switched-R-MOSFET-C filters is presented. The technique is demonstrated through simulations and backed by analytical expressions for first order active RC and second order biquad filters; the improvement in clock distortion is presented and compared with previously reported architectures. The proposed harmonic cancellation technique shows an improvement of more than 33 dB over previous architectures without compromising the tuning range.