Jiahao Zhao

This article presents a 0.6-V high-efficiency Bluetooth low-energy (BLE) transmitter (TX) in 65-nm CMOS with following features: 1) a sub-mW hybrid phase-locked loop (PLL) for closed-loop modulation with a resistor digital-to-analog converter (RDAC)-based common-mode (CM) ripple cancellation to suppress reference spur; 2) a low-power switching current-source (SCS) digital/voltage-controlled oscillator (D/VCO) with a shared bias resistor for a differential varactor to cancel resistor noise; 3) a duty-cycle-controlled class-E/F₂ digital power amplifier (PA) to suppress third-harmonic distortion (HD3) without degrading PA efficiency; and 4) a calibration-free 1-bit $\Delta \Sigma $ high-pass modulation with finite-impulse response (FIR) filtering to overcome the nonlinearity issue of a low-voltage digitally controlled oscillator (DCO) in two-point modulation. The proposed TX implemented in 65-nm CMOS achieves a high system efficiency of 25.1% at 0-dBm output with closed-loop modulation. The reference spur level is reduced by more than 18 dB in both PLL and BLE spectrum. The TX exhibits second-harmonic distortion (HD2) and HD3 values of −50.1 and −52.1 dBm, respectively. The proposed TX satisfies BLE requirements while occupying a compact area of 0.46 mm² without external components.

This article describes a polar phase-tracking receiver (PT-RX) architecture that can work with various modulations including differential phase shift keying (DPSK), amplitude phase shift keying (APSK), and quadrature amplitude modulation (QAM). By employing a two-point injection method in a wideband digital phase-locked loop (DPLL), the proposed polar PT-RX performs various demodulations without requiring quadrature signal generation or a multi-bit analog-to-digital converter (ADC). Compared with existing PT-RXs, the proposed architecture not only overcomes the trade-off between frequency pulling and image rejection but also provides the equivalent constant gain of a digitally controlled oscillator (DCO) for robust demodulation. A prototype 5.8-mW 2.4-GHz polar PT-RX is implemented in 65-nm CMOS and performs demodulations of 8-DPSK at 1.5 Mb/s, 16-QAM at 2 Mb/s and 32-APSK at 2.5 Mb/s, achieving a sensitivity of −81, - 68, and −64 dBm, respectively.

This article presents an ultra-low voltage (ULV) fractional- $N$ hybrid phase-locked loop (PLL) without requiring bias current. A time-interleaved flip-flop phase detector (TI-FFPD) with duty-cycle-based phase detection is employed to achieve high linearity and low reference spur. A passive-intensive voltage-mode phase interpolator (VPI) with a supply-immune voltage scaling topology is proposed for $\Delta\Sigma$ quantization noise (Q-noise) reduction without gain or linearity calibration. A hybrid PLL (HPLL) that consists of a pseudo-differential analog proportional path and a digital integral path is implemented in 28-nm CMOS. The HPLL exhibits 607-fs $_{\mathrm{rms}}$ jitter and $-$ 59-dBc in-band fractional spur at 2.42-GHz output and consumes 0.78-mW power from a 0.5-V supply, achieving the best figure of merit (FoM $_{\mathrm{JIT}}$ ) of $-$ 245.4 dB among low-voltage ( $V_{\mathrm{DD}}$ $<$ 0.8 V) fractional- $N$ PLLs.

This paper describes a crystal-less heterodyne phase-tracking receiver (PTRX) architecture that offers a wide tracking range, flexible yet robust loop dynamics, and a 1-bit demodulation output. Unlike the sliding-IF PTRX, a nested integer-N bang-bang phase-locked loop (BBPLL) is implemented within the PTRX to enhance the tracking range by taking the output of an intermediate-frequency (IF) voltage-controlled oscillator (VCO) as an input. The BBPLL also performs phase-to-digital conversion with an oversampled 1-bit digital output. To further improve the demodulation performance, a dual-path injection method with extra control inversion is employed. In the proposed heterodyne PTRX, a phase offset over frequency variation is minimized in the IF mixer. As a result, the mixer-based phase detector in the proposed PTRX has lower gain variation over frequency changes even with a type-I loop, resulting in stable loop dynamics. In this paper, the frequency-tracking and phase-tracking properties of the PTRX are analyzed in view of the jitter transfer and jitter tolerance characteristics of a clock-and-data recovery (CDR) circuit for the first time. The proposed 2.4-GHz PTRX is implemented in 65-nm CMOS, consuming 3.0 mW from a 0.9-V supply. The receiver achieves a sensitivity of –83 dBm at 1 Mb/s.