Hossein Mohammadnezhad

A novel high-speed wireless transmitter (TX) architecture is presented that directly transforms incoming data bits into high-order 4M-quadrature amplitude modulation (QAM) constellation by adding multiple quadrature phase shift keying (QPSK) signals with appropriate amplitude ratios. The costly high-speed digital-to-analog converters (DACs) in conventional TXs are thus completely avoided, resulting in a highly integrated solution amenable to ultra-high speeds and operating frequencies. Design tradeoffs are analyzed in detail. Based on this article, a TX prototype at 115-GHz carrier frequency implementing the 16QAM direct-modulation scheme is fabricated in a 180-nm SiGe BiCMOS process (fMAX = 270 GHz). Wireless testing at a 20-cm distance with 25-dBi horn antennas on both transmitting and receiving side measures 20-Gb/s data rate with an error vector magnitude (EVM) of -15.8 dB and modulated output power of +1 dBm. The TX consumes 520 mW of power and occupies 3.17 mm² of active area.

This paper presents the theory, design, and implementation of an 8PSK direct-demodulation receiver based on a novel multi-phase RF-correlation concept. The output of this RF-to-bits receiver architecture is demodulated bits, obviating the need for power-hungry high-speed-resolution data converters. A single-channel 115-135-GHz receiver prototype was fabricated in a 55-nm SiGe BiCMOS process. A max conversion gain of 32 dB and a min noise figure (NF) of 10.3 dB were measured. A data rate of 36 Gb/s was wirelessly measured at 30-cm distance with the received 8PSK signal being directly demodulated on-chip at a bit-error rate (BER) of 1e-6. The measured receiver sensitivity at this BER is -41.28 dBm. The prototype occupies 2.5 x 3.5 mm² of die area, including PADs and test circuits (2.5-mm² active area), and consumes a total dc power of 200.25 mW.

This paper presents an analysis and design of a partially overlapped beamforming-multiple-input multiple-output (MIMO) architecture capable of achieving higher beamforming and spatial multiplexing gains with lower number of elements compared to conventional architectures. As a proof of concept, a four-element beamforming-MIMO receiver (RX) covering 64-67-GHz frequency band (the FCC's newly allocated 64-71-GHz frequency band for high-speed wireless links between small cells) enabling two-stream concurrent reception is designed and measured. By partitioning the RX elements into two clusters and partially overlapping these clusters to create two three-element beamformers, both phased array (coherent beamforming) as well as MIMO (spatial multiplexing) features are simultaneously acquired. 6-bit phase shifters with 360° phase control and 5-bit VGAs with 11-dB range are designed to enable steering of the two RX clusters toward two arbitrary angular locations corresponding to two users. Fabricated in a 130-nm SiGe BiCMOS process, the RX achieves a 30.15-dB maximum direct conversion gain and a 9.8-dB minimum noise figure across 548-MHz IF bandwidth. S-parameter-based array factor measurements verify spatial filtering of the interference and spatial multiplexing in this RX chip.

A wideband, low-loss balun-based differential power splitter is studied. The use of lumped double-tuned baluns as key building blocks within a splitter leads to a wideband operation, while avoiding signal crossovers and the detrimental effects associated with them. Moreover, the lack of multiple λ/4 transmission-line (T-line) sections results in an area-efficient and low-loss structure. A demonstration of this design approach comprising a differential 1-to-4 splitter was EM-simulated at 120 GHz in a 65nm CMOS process. Full-wave EM-simulations, verifying the performance of this splitter, show a minimum in-band insertion loss of 8.3 dB and a port-to-port isolation of 10 dB (or better) across a 3-dB bandwidth of 40 GHz.

The analysis, design, and implementation of a 50-Gb/s transimpedance amplifier (TIA) in a 0.13-μm SiGe BiCMOS process are presented. The proposed TIA, designed for use in a single-channel optical communication network, is comprised of three stages including: 1) a shunt-peaked, shunt-series feedback stage incorporating a transformer-based positive feedback; 2) an RC-degenerated common-emitter stage; and 3) an inductively degenerated emitter follower. The TIA chip integrates an on-chip 100-fF input capacitor to emulate the photo-detector junction capacitor, and achieves a measured transimpedance gain of 41 dBΩ and an input-referred current-noise spectral density of 39.8 pA/√Hz over a 50-GHz bandwidth. The TIA achieves an open eye at 50 Gbps with random jitter of 2.3-ps rms (including the jitter contribution of the test fixture). The prototype chip occupies 0.58 mm² (including pads) of die area and dissipates 24 mW of dc power from a 2-V supply voltage (i.e., less than 0.5 pJ/bit).