Yee-Chia Yeo
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
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Yee-Chia Yeo has a total of 406 co-authors. Here are the top co-authors by number of shared publications:
Wei Wang
Department of Electrical and Computer Engineering, National University of Singapore 117576, Singapore
35 shared publicationsGanesh Samudra
Dept. of Electrical and Computer Engineering, National University of Singapore (NUS), 117576, Singapore
31 shared publicationsQian Zhou
Department of Electrical and Computer Engineering, National University of Singapore, 117576, Singapore
31 shared publicationsXiao Gong
Department of Electrical and Computer Engineering, National University of Singapore, 117576 Singapore
31 shared publicationsGanesh S. Samudra
Department of Electrical and Computer Engineering, National University of Singapore, Singapore
29 shared publicationsKian-Ming Tan
Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore
25 shared publications
Latest Publications
- 3 December 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 27.1.1-27.1.4
Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
To continue contacted gate pitch scaling, transistor with improved electrostatics, gate stack innovation, and appropriate contact scheme along with improved process control to reduce variability are all indispensable factors. As gate pitch scales into the sub-50nm regime, electrostatics of FinFET architecture, spacer material, and traditional contact scheme all approach their engineering limits. Here we report a leading-edge CMOS technology developed at 45nm contacted gate pitch that successfully incorporates optimized fin profile, low-k spacer and self-aligned contact scheme. The process robustness is validated by a logic test chip with >3.5 billion transistor gate count and fully functioning 256Mb HC/HD SRAM macros. The demonstrated high-density SRAM cell size of $0.0199 \mu \mathrm{m}^{2}$ is the smallest reported to date.- 3 December 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 27.1.1-27.1.4
Critical Process Features Enabling Aggressive Contacted Gate Pitch Scaling for 3nm CMOS Technology and Beyond
To continue contacted gate pitch scaling, transistor with improved electrostatics, gate stack innovation, and appropriate contact scheme along with improved process control to reduce variability are all indispensable factors. As gate pitch scales into the sub-50nm regime, electrostatics of FinFET architecture, spacer material, and traditional contact scheme all approach their engineering limits. Here we report a leading-edge CMOS technology developed at 45nm contacted gate pitch that successfully incorporates optimized fin profile, low-k spacer and self-aligned contact scheme. The process robustness is validated by a logic test chip with >3.5 billion transistor gate count and fully functioning 256Mb HC/HD SRAM macros. The demonstrated high-density SRAM cell size of $0.0199 \mu \mathrm{m}^{2}$ is the smallest reported to date.- 4 June 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (7) , 2690-2696
A Ladder Transmission Line Model for the Extraction of Ultralow Specific Contact Resistivity—Part II: Experimental Verification
In the first part of this two-part article, a ladder transmission line model (LTLM), featuring elimination of parasitic metal resistances and high accuracy for extracting specific contact resistivity ρc, is developed and verified by simulation. In Part II, the LTLM is applied experimentally to Ni contacts formed on the heavily Ga-doped Ge0.95Sn0.05 film. Two types of Ni/p⁺-Ge0.95Sn0.05 LTLM structures, single-cell and multicell LTLMs, are fabricated. Ultralow ρc values of 8.6 ± 2 x 10⁻¹⁰ Ω-cm² and 1.1 ± 0.3 x 10⁻⁹ Ω-cm² are extracted from the single-cell and multicell LTLMs, respectively. The good agreement of the extracted ρc from the single-cell and multicell structures validates the ρc extraction by the LTLM. ρc is also extracted by using refined transmission line model (RTLM). In contrast, the extracted ρc by the RTLM is more than two times larger due to the ignored parasitic metal resistance. The proposed LTLM is a useful tool for an accurate assessment of ρc in advanced contact technology.
- 4 June 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (7) , 2690-2696
A Ladder Transmission Line Model for the Extraction of Ultralow Specific Contact Resistivity—Part II: Experimental Verification
In the first part of this two-part article, a ladder transmission line model (LTLM), featuring elimination of parasitic metal resistances and high accuracy for extracting specific contact resistivity ρc, is developed and verified by simulation. In Part II, the LTLM is applied experimentally to Ni contacts formed on the heavily Ga-doped Ge0.95Sn0.05 film. Two types of Ni/p⁺-Ge0.95Sn0.05 LTLM structures, single-cell and multicell LTLMs, are fabricated. Ultralow ρc values of 8.6 ± 2 x 10⁻¹⁰ Ω-cm² and 1.1 ± 0.3 x 10⁻⁹ Ω-cm² are extracted from the single-cell and multicell LTLMs, respectively. The good agreement of the extracted ρc from the single-cell and multicell structures validates the ρc extraction by the LTLM. ρc is also extracted by using refined transmission line model (RTLM). In contrast, the extracted ρc by the RTLM is more than two times larger due to the ignored parasitic metal resistance. The proposed LTLM is a useful tool for an accurate assessment of ρc in advanced contact technology.
- 19 May 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (7) , 2682-2689
A Ladder Transmission Line Model for the Extraction of Ultralow Specific Contact Resistivity—Part I: Theoretical Design and Simulation Study
A ladder transmission line model (LTLM) that features capability to eliminate parasitic metal resistance from contact metal and access electrodes, a simple fabrication process, and a sub-10⁻¹⁰ Ω· cm² resolution is demonstrated for accurate extraction of the specific contact resistivity ρc. The proposed LTLM is verified by technology computer-aided design (TCAD) simulation and a two-layer distributed-resistor network model. After eliminating the parasitic metal resistance, the current spreading and crowding effects are the main factors that contribute to the extraction error in LTLM. The effects of current spreading and crowding on the extraction of ρc in LTLM are further quantitatively analyzed and design guidelines to achieve a sub-10⁻¹⁰ Ω · cm² resolution of ρc extraction are provided. The details of theoretical modeling and simulation of LTLM are documented in Part I. The experimental demonstration of extracting sub-10⁻⁹ Ω · cm² ρc using the proposed LTLM is provided in Part II.
- 19 May 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (7) , 2682-2689
A Ladder Transmission Line Model for the Extraction of Ultralow Specific Contact Resistivity—Part I: Theoretical Design and Simulation Study
A ladder transmission line model (LTLM) that features capability to eliminate parasitic metal resistance from contact metal and access electrodes, a simple fabrication process, and a sub-10⁻¹⁰ Ω· cm² resolution is demonstrated for accurate extraction of the specific contact resistivity ρc. The proposed LTLM is verified by technology computer-aided design (TCAD) simulation and a two-layer distributed-resistor network model. After eliminating the parasitic metal resistance, the current spreading and crowding effects are the main factors that contribute to the extraction error in LTLM. The effects of current spreading and crowding on the extraction of ρc in LTLM are further quantitatively analyzed and design guidelines to achieve a sub-10⁻¹⁰ Ω · cm² resolution of ρc extraction are provided. The details of theoretical modeling and simulation of LTLM are documented in Part I. The experimental demonstration of extracting sub-10⁻⁹ Ω · cm² ρc using the proposed LTLM is provided in Part II.
- 9 October 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Emerging and Selected Topics in Power Electronics
- Vol. 8 (1) , 31-41
All-GaN Power Integration: Devices to Functional Subcircuits and Converter ICs
This paper reports the Au-free GaN power integration platform and a complete integration scheme from devices to functional sub-circuits, and to application-oriented GaN converter ICs. The design and experimental demonstration of all GaN DC-DC converter IC with high level of integration is presented. Through the developed GaN power integration platform, devices are monolithically integrated and functional sub-circuits are demonstrated, which have realized expected application-oriented functions and are feasible for high-level integration. The all GaN converter IC with monolithically integrated high-side gate driver, pulse width modulation (PWM) feedback controller and over-current protection circuits is proposed, numerically analyzed, experimentally demonstrated and characterized. It can realize stable 10 V output with constant output ripples below 4% from 15-30 V input line voltage. Stable output with constant ripples can be maintained according to designed feedback control when input and load conditions are abruptly changed. When subjected to over-current incident, the converter IC can be protected according to desired over-current threshold values within one duty cycle period. The developed all GaN power integration platform, together with functional sub-circuits and DC-DC converter IC, can be a practical verification of all GaN IC scheme oriented towards power conversion application, and a useful reference for all GaN IC designs.
- 9 October 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Emerging and Selected Topics in Power Electronics
- Vol. 8 (1) , 31-41
All-GaN Power Integration: Devices to Functional Subcircuits and Converter ICs
This paper reports the Au-free GaN power integration platform and a complete integration scheme from devices to functional sub-circuits, and to application-oriented GaN converter ICs. The design and experimental demonstration of all GaN DC-DC converter IC with high level of integration is presented. Through the developed GaN power integration platform, devices are monolithically integrated and functional sub-circuits are demonstrated, which have realized expected application-oriented functions and are feasible for high-level integration. The all GaN converter IC with monolithically integrated high-side gate driver, pulse width modulation (PWM) feedback controller and over-current protection circuits is proposed, numerically analyzed, experimentally demonstrated and characterized. It can realize stable 10 V output with constant output ripples below 4% from 15-30 V input line voltage. Stable output with constant ripples can be maintained according to designed feedback control when input and load conditions are abruptly changed. When subjected to over-current incident, the converter IC can be protected according to desired over-current threshold values within one duty cycle period. The developed all GaN power integration platform, together with functional sub-circuits and DC-DC converter IC, can be a practical verification of all GaN IC scheme oriented towards power conversion application, and a useful reference for all GaN IC designs.
- Open Access
- 11 September 2019
- Published by Optica Publishing Group in Optics Express
- Vol. 27 (19) , 26924-26939
Integrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band
High-performance GeSn multiple-quantum-well (MQW) photodiode is demonstrated on a 200 mm Ge-on-insulator (GeOI) photonics platform for the first time. Both GeSn MQW active layer stack and Ge layer (top Ge layer of GeOI after bonding) were grown using a single epitaxy step on a standard (001)-oriented Si substrate (donor wafer) using a reduced pressure chemical vapor deposition (RPCVD). Direct wafer bonding and layer transfer technique were then employed to transfer the GeSn MQW device layers and Ge layer to a 200 mm SiO2-terminated Si handle substrate. The surface illuminated GeSn MQW photodiode realized on this platform exhibits an ultra-low leakage current density of 25 mA/cm2 at room temperature and an enhanced photo sensitivity at 2 μm of 30 mA/W as compared to a GeSn MQW photodiode on Si at 2 μm. The underlying GeOI platform enables monolithic integration of a complete suite of photonics devices operating at 2 μm band, including GeOI strip waveguides, grating couplers, micro-ring modulators, Mach–Zehnder interferometer modulators, etc. In addition, Ge CMOS circuits can also be realized on this common platform using a “photonic-first and electronic-last” processing approach. In this work, as prototype demonstration, both Ge p- and n-channel fin field-effect transistors (FinFETs) were realized on GeOI simultaneously with decent static electrical characteristics. Subthreshold swings of 150 and 99 mV/decade at |VD| = 0.1 V and drive currents of 91 and 10.3 μA/μm at |VG-VTH| = 1 V and |VD| = 0.75 V were achieved for p- and n-FinFETs, respectively. This works illustrates the potential of integrating GeSn (as photo detection material) on GeOI platform for Ge-based optoelectronics integrated circuits (OEICs) targeting communication applications at 2 μm band.
- 11 September 2019
- Published by Optica Publishing Group in Optics Express
- Vol. 27 (19) , 26924-26939
Open AccessIntegrating GeSn photodiode on a 200 mm Ge-on-insulator photonics platform with Ge CMOS devices for advanced OEIC operating at 2 μm band
High-performance GeSn multiple-quantum-well (MQW) photodiode is demonstrated on a 200 mm Ge-on-insulator (GeOI) photonics platform for the first time. Both GeSn MQW active layer stack and Ge layer (top Ge layer of GeOI after bonding) were grown using a single epitaxy step on a standard (001)-oriented Si substrate (donor wafer) using a reduced pressure chemical vapor deposition (RPCVD). Direct wafer bonding and layer transfer technique were then employed to transfer the GeSn MQW device layers and Ge layer to a 200 mm SiO2-terminated Si handle substrate. The surface illuminated GeSn MQW photodiode realized on this platform exhibits an ultra-low leakage current density of 25 mA/cm2 at room temperature and an enhanced photo sensitivity at 2 μm of 30 mA/W as compared to a GeSn MQW photodiode on Si at 2 μm. The underlying GeOI platform enables monolithic integration of a complete suite of photonics devices operating at 2 μm band, including GeOI strip waveguides, grating couplers, micro-ring modulators, Mach–Zehnder interferometer modulators, etc. In addition, Ge CMOS circuits can also be realized on this common platform using a “photonic-first and electronic-last” processing approach. In this work, as prototype demonstration, both Ge p- and n-channel fin field-effect transistors (FinFETs) were realized on GeOI simultaneously with decent static electrical characteristics. Subthreshold swings of 150 and 99 mV/decade at |VD| = 0.1 V and drive currents of 91 and 10.3 μA/μm at |VG-VTH| = 1 V and |VD| = 0.75 V were achieved for p- and n-FinFETs, respectively. This works illustrates the potential of integrating GeSn (as photo detection material) on GeOI platform for Ge-based optoelectronics integrated circuits (OEICs) targeting communication applications at 2 μm band.
- 6 June 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 66 (7) , 3086-3092
Elimination of the Parasitic Metal Resistance in Transmission Line Model for Extraction of Ultralow Specific Contact Resistivity
A metal-resistance-aware transmission line model (MRA-TLM) is developed to eliminate the parasitic metal resistance from the extraction of specific contact resistivity ρc in the metal/semiconductor contact. The proposed MRA-TLM is verified by Synopsys technology computer-aided design (TCAD) simulation, and a superior extraction accuracy as compared to the conventional TLM-based method is achieved. The proposed MRA-TLM is experimentally demonstrated in the metal/p⁺-Ge0.95n0.05 (p⁺-GeSn) contacts. Ultralow ρc values of 7.5 x 10⁻¹⁰ and 2.1 x 10⁻⁹ Ω · cm² are extracted by MRA-TLM for Ni/p⁺-GeSn and Ti/p⁺-GeSn contacts, respectively, which are in good agreement with 9.5 x 10⁻¹⁰ and 2.6 x 10⁻⁹ Ω · cm² extracted numerically by the two-layer distributed-resistor-network model (TDM), qualifying the proposed MRA-TLM for the extraction of ultralow ρ c down to sub-10⁻⁹ Ω · cm² regime. In contrast, the ρc extracted by the conventional TLM-based method is more than three times higher due to the parasitic metal resistance.
- 6 June 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 66 (7) , 3086-3092
Elimination of the Parasitic Metal Resistance in Transmission Line Model for Extraction of Ultralow Specific Contact Resistivity
A metal-resistance-aware transmission line model (MRA-TLM) is developed to eliminate the parasitic metal resistance from the extraction of specific contact resistivity ρc in the metal/semiconductor contact. The proposed MRA-TLM is verified by Synopsys technology computer-aided design (TCAD) simulation, and a superior extraction accuracy as compared to the conventional TLM-based method is achieved. The proposed MRA-TLM is experimentally demonstrated in the metal/p⁺-Ge0.95n0.05 (p⁺-GeSn) contacts. Ultralow ρc values of 7.5 x 10⁻¹⁰ and 2.1 x 10⁻⁹ Ω · cm² are extracted by MRA-TLM for Ni/p⁺-GeSn and Ti/p⁺-GeSn contacts, respectively, which are in good agreement with 9.5 x 10⁻¹⁰ and 2.6 x 10⁻⁹ Ω · cm² extracted numerically by the two-layer distributed-resistor-network model (TDM), qualifying the proposed MRA-TLM for the extraction of ultralow ρ c down to sub-10⁻⁹ Ω · cm² regime. In contrast, the ρc extracted by the conventional TLM-based method is more than three times higher due to the parasitic metal resistance.
- 14 February 2019
- Published by Optica Publishing Group in Optics Express
- Vol. 27 (4) , 5798-5813
High-speed photo detection at two-micron-wavelength: technology enablement by GeSn/Ge multiple-quantum-well photodiode on 300 mm Si substrate
We report high-speed photo detection at two-micron-wavelength achieved by a GeSn/Ge multiple-quantum-well (MQW) p-i-n photodiode, exhibiting a 3-dB bandwidth (f3-dB) above 10 GHz for the first time. The epitaxy of device layer stacks was performed on a standard (001)-oriented 300 mm Si substrate by using reduced pressure chemical vapor deposition (RPCVD). The results showed promise for large-scale manufacturing. To our knowledge, this is also the first photodiodes-on-Si with direct radio-frequency (RF) measurement to quantitatively confirm high-speed functionality with tens of GHz f3-dB at 2 µm, which is considered as a promising candidate for the next data communication window. This work illustrates the potential for using GeSn to extend the utility of Si photonics in 2 µm band integrated optical transceivers for communication applications.
- 14 February 2019
- Published by Optica Publishing Group in Optics Express
- Vol. 27 (4) , 5798-5813
High-speed photo detection at two-micron-wavelength: technology enablement by GeSn/Ge multiple-quantum-well photodiode on 300 mm Si substrate
We report high-speed photo detection at two-micron-wavelength achieved by a GeSn/Ge multiple-quantum-well (MQW) p-i-n photodiode, exhibiting a 3-dB bandwidth (f3-dB) above 10 GHz for the first time. The epitaxy of device layer stacks was performed on a standard (001)-oriented 300 mm Si substrate by using reduced pressure chemical vapor deposition (RPCVD). The results showed promise for large-scale manufacturing. To our knowledge, this is also the first photodiodes-on-Si with direct radio-frequency (RF) measurement to quantitatively confirm high-speed functionality with tens of GHz f3-dB at 2 µm, which is considered as a promising candidate for the next data communication window. This work illustrates the potential for using GeSn to extend the utility of Si photonics in 2 µm band integrated optical transceivers for communication applications.
- 1 January 2019
- Published by Optica Publishing Group
- p. STu4J.1
Enhanced Photo Response at Two-micron-wavelength Using GeSn/Ge Multiple-Quantum-Well Waveguide
GeSn multiple-quantum-well rib waveguide on Si substrate was fabricated with vertical p-i-n photodiode structure and was characterized at two-micron-wavelength. Enhanced external photo response was achieved as compared to surface-illuminated counterparts, thanks to the waveguide scheme.
- 1 January 2019
- Published by Optica Publishing Group
- p. STu4J.1
Enhanced Photo Response at Two-micron-wavelength Using GeSn/Ge Multiple-Quantum-Well Waveguide
GeSn multiple-quantum-well rib waveguide on Si substrate was fabricated with vertical p-i-n photodiode structure and was characterized at two-micron-wavelength. Enhanced external photo response was achieved as compared to surface-illuminated counterparts, thanks to the waveguide scheme.
- 1 January 2019
- Published by Optica Publishing Group
- p. STu4J.2
Formation of GeSn Multiple-Quantum-Well Microdisks on Insulating Platform toward Lasing Applications
GeSn multiple-quantum-well microdisks are demonstrated on an 8-inch insulating platform, which was formed using direct wafer bonding technique. Whispering-gallery modes are identified through FDTD simulation, showing potential of such ultra-compact cavities for Group-IV lasing.
- 1 January 2019
- Published by Optica Publishing Group
- p. STu4J.2
Formation of GeSn Multiple-Quantum-Well Microdisks on Insulating Platform toward Lasing Applications
GeSn multiple-quantum-well microdisks are demonstrated on an 8-inch insulating platform, which was formed using direct wafer bonding technique. Whispering-gallery modes are identified through FDTD simulation, showing potential of such ultra-compact cavities for Group-IV lasing.