Amol Domaji Gaidhane

Cryogenic CMOS is a promising technology for high performance computing due to its improvement in subthreshold slope, carrier mobilities and reduced wire resistance. The threshold voltage (V_th) increase at 77K can be mitigated by metal gate work function (PHIG) engineering to achieve matched off current (I_off) further enhancing the device performance allowing us to operate at very low supply voltage thereby reducing the Energy Delay Product (EDP). However, the effect of variation on noise margins of static random access memories (SRAM) deploying these matched I_off devices is very prominent especially at low supply voltages (V_dd) limiting its scaling. In this work, we propose a framework to perform V_th retargeting for cryogenic SRAM for improving noise margins in high performance cryogenic SRAM cells under variation. The proposed framework comprises of a Monte-Carlo engine which performs statistical analysis and DC characterization and a backend processing engine to analyze noise margins and tune the PHIG. To demonstrate the framework, we use calibrated 14nm FinFET models at 300K and 77K. First, we analyze the logic blocks using iso-I_off devices, which yield up to 3x improvement in delay at iso-energy and a 4.5x reduction in energy at iso-delay. Next, we study the effect of V_th variation on the device currents. Finally, the framework is deployed to tune PHIG, and results show that it can enhance the noise margins by 23%, 31% and 19% for hold, read and write operations respectively at 77K compared to iso-I_off devices. Further, a 1kb SRAM array has been simulated using iso-I_off tuned peripherals and framework tuned SRAM cells, and it shows 5.4x reduction in read/write energies along with 1.2x delay reduction and better noise margins at 77K compared to 300K.

This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.

Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultra-steep sub-threshold slope and ultra-low leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14nm TCAD simulation and our experimental FinFET data from 300K to 77K. These models are scalable with temperatures from 300K down to 77K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than 15× reduction in total energy consumption is demonstrated at 77K for the iso-Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.

Compact models for CMOS transistors usually have many fitting parameters to accurately capture the device properties, especially for the cutting-edge CMOS technology. As a result, parameter extraction of compact models requires a lot of expertise and engineering time. To overcome this barrier, we propose a new machine learning approach, graph-based compact model (GCM), to automate parameter extraction with high efficiency. GCM starts from a core set of physical equations, such as long-channel surface potential with semi-empirical analytic equations for short-channel effects. It then aggregates these physical models through graph neural networks (GNNs) to predict the final device behavior. In this approach, the analytic equations preserve physical dependencies on process and bias conditions, while the neural networks in GCM enable model training driven by a small set of measurement data. Using GCM, we demonstrate parameter extraction with high accuracy for dc and ac data from GlobalFoundries 12 nm FinFET technology. We further incorporate channel length and temperature dependence in GCM. The generation of a full GCM model card is less than 5 min, all automated through the back propagation process. Finally, GCM is implemented in Verilog-A and passes Si2 benchmark tests, ensuring model continuity and quality in circuit simulations.

General-purpose multiply-accumulate (MAC) accelerators have become inevitable in the internet-of-things (IoT) edge devices for performing computationally intensive tasks such as deep learning, signal processing, and combinatorial optimization. The throughput and the energy-efficiency of the conventional digital processors and MAC accelerators are limited due to their sparse design owing to the von-Neumann architecture. Although mixed-signal time-mode MAC accelerators utilizing emerging non-volatile memories appear promising owing to their ability to perform in-memory MAC operation via the physical laws, their application is limited due to their incompatibility and complex integration with the CMOS process, high sensitivity to process variations, large operating voltage/cell currents, etc. To mitigate these issues, in this work, we propose a time-mode MAC accelerator based on ferroelectric-FinFETs with CMOS-compatible doped- ${\text{HfO}_\text{2}}$ in the gate-stack. Our rigorous analysis reveals a trade-off between the performance metrics such as computational precision, area-and energy-efficiency of the proposed MAC accelerator. Therefore, we provide the necessary design guidelines to further optimize the performance. Extensive design space exploration and simulations exploiting an experimentally calibrated compact model for the doped ${\text{HfO}_\text{2}}$ ferroelectric capacitor along with experimentally calibrated baseline FinFET model for 14 nm-technology indicates that the proposed MAC accelerator exhibits an energy-efficiency of 800 TeraOperations/Joule, a considerably high area-efficiency of 12.607 bits/ $\mu\text{m}^{\text{2}}$ (including I/O peripheral circuitry), and a throughput of 2.5 TeraOp/s while supporting a 4-bit MAC operation for a square weight matrix of size 200 $\times$ 200 which is sufficient for realistic inference tasks.

In this article, we present a physics-based compact model of flicker noise (low-frequency noise) in ferroelectric (FE) field-effect transistors (FETs). This model predicts the noise due to charge trapping/de-trapping in the FE/dielectric interface accounting for both carrier number fluctuations and correlated mobility fluctuations in the channel. This model can work with any FE framework and has been tested with Landau based as well as nucleation-limited-switching (NLS)-based cores. The effect of FE thickness scaling is also captured. The model is validated for both logic and memory devices with TCAD as well as experimental measurements.

In this paper, we develop a Verilog-A implementable compact model for the dynamic switching of ferroelectric FinFETs (Fe-FinFETs) for asymmetric non-periodic input signals. We use the multi-domain Preisach Model to capture the saturated P-E loop of the ferroelectric capacitors. In addition to the saturation loop, we model the history dependent minor loop paths in the P-E by tracing input signals’ turning points. To capture the input signals’ turning points, we propose an RC circuit based approach in this work. We calibrate our proposed model with the experimental data, and it accurately captures the history effect and minor loop paths of the ferroelectric capacitor. Furthermore, the elimination of storage of each turning point makes the proposed model computationally efficient compared with the previous implementations. We also demonstrate the unique electrical characteristics of Fe-FinFETs by integrating the developed compact model of Fe-Cap with the BSIM-CMG model of the 7nm FinFET.

Ferroelectric field-effect transistor (FeFET)-based circuit implementation mimicking FitzHugh-Nagumo neuron is proposed in this work. The proposed circuit is shown to mimic biological neuron properties, such as excitation block and anodal break excitation which are not mimicked by an integrate and fire neuron model. We also show a winner-take-all circuit that can be used with this proposed neuron implementation. The neuron implementation requires just one FeFET, three baseline field-effect transistors, and one capacitor, making it area and energy-efficient. The neuron circuit, with minimum sized transistors, consumes approximately 10 pJ per spike. The neuron’s energy consumption per spike can be reduced to as low as 100 fJ by designing some of the transistors with aspect ratio less than one.

In this article, we exploit the negative-capacitance (NC) property of ferroelectrics for high-voltage (HV) applications. We present rigorous analysis and new physical insights into the operation of the NC-based MOSFET with a ferroelectric layer in the gate-stack and drain-extended architecture [NC-drain extended metal oxide semiconductor (DEMOS)]. We show that the voltage amplification effect generated by the NC property of the ferroelectric layer boosts the on-current and transconductance, which can improve the HV switching and analog performance over conventional DEMOS devices. However, several issues ascribed to the drain-extended structure may arise at large ferroelectric thicknesses, including elevated quasi-saturation and impact ionization effects that limit the benefits of NC. We further investigate the switching and analog figures of merit of NC-DEMOS. We show that the NC-DEMOS offers a smaller on-resistance without any considerable reduction in the breakdown voltage. Moreover, the NC-DEMOS is found to provide a larger analog gain compared with that of the conventional DEMOS, although with a smaller intrinsic cutoff frequency.