Assessing Negative-Capacitance Drain-Extended Technology for High-Voltage Switching and Analog Applications
- 29 December 2020
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 68 (2) , 679-687
Abstract
In this article, we exploit the negative-capacitance (NC) property of ferroelectrics for high-voltage (HV) applications. We present rigorous analysis and new physical insights into the operation of the NC-based MOSFET with a ferroelectric layer in the gate-stack and drain-extended architecture [NC-drain extended metal oxide semiconductor (DEMOS)]. We show that the voltage amplification effect generated by the NC property of the ferroelectric layer boosts the on-current and transconductance, which can improve the HV switching and analog performance over conventional DEMOS devices. However, several issues ascribed to the drain-extended structure may arise at large ferroelectric thicknesses, including elevated quasi-saturation and impact ionization effects that limit the benefits of NC. We further investigate the switching and analog figures of merit of NC-DEMOS. We show that the NC-DEMOS offers a smaller on-resistance without any considerable reduction in the breakdown voltage. Moreover, the NC-DEMOS is found to provide a larger analog gain compared with that of the conventional DEMOS, although with a smaller intrinsic cutoff frequency.Keywords
Funding Information
- SwarnaJayanti Fellowship (DST/SJF/ETA-02/2017-18)
- Fund for Improvement of S&T Infrastructure in Higher Educational Institutions (FIST) Scheme, Department of Science and Technology, Government of India (SR/FST/ETII-072/2016)
This publication has 32 references indexed in Scilit:
- Drain Extended Tunnel FET—A Novel Power Transistor for RF and Switching ApplicationsIEEE Transactions on Electron Devices, 2016
- Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model ValidationIEEE Transactions on Electron Devices, 2016
- Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model DescriptionIEEE Transactions on Electron Devices, 2016
- Room-Temperature Negative Capacitance in a Ferroelectric–Dielectric Superlattice HeterostructureNano Letters, 2014
- Experimental Observation of Negative Capacitance in Ferroelectrics at Room TemperatureNano Letters, 2014
- Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructuresApplied Physics Letters, 2011
- Analysis and Fabrication of an LDMOS With High-Permittivity DielectricIEEE Electron Device Letters, 2011
- Substrate current characterization and optimization of high voltage LDMOS transistorsSolid-State Electronics, 2008
- Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage2001
- High-voltage drain extended MOS transistors for 0.18-μm logic CMOS processIEEE Transactions on Electron Devices, 2001