Longyang Lin

Compact machine vision with wide-field-of-view (FOV) three-dimensional (3D) motion perception is critical for intelligent, autonomous systems that interact dynamically with environments. Conventional systems, which combine wide-FOV and binocular cameras with complex 3D processing hardware, suffer from bulkiness, high energy consumption, and latency. While emerging neuromorphic in‑sensor computing approaches hold great promise, current neuromorphic vision devices are inherently limited: they lose depth information during 3D‑to‑2D projection, suffer from narrow detection angles, and lack 3D motion-processing capability. Here, we present a planar anisotropic optoelectronic resistive random-access memory (AORRAM) device based on a ZnO nanowire array with an engineered axial defect gradient. It achieves wide-FOV (up to 140°), anisotropic, multilevel non-volatile optical resistive switching. Using its intrinsic anisotropy, we construct a hardware system for robust in-sensor monocular motion depth perception and localization. Integrated with a gated recurrent unit, the system enables compact, low-power 3D motion recognition, achieving 95.41% accuracy under noisy conditions.

Edge devices capable of running artificial intelligence (AI) applications have seen a surge in demand for energy-efficient and high-throughput computation. In this study, a 22-nm edge–AI processor, incorporating an accelerator with error-free Booth-value-confined (BVC) multiprecision (MP) multiplier and near-memory computing (NMC), is introduced to accelerate neural networks (NNs). It has the following three major features. First, a BVC MP multiplier based on radix-8 Booth (R8B) is introduced to reduce computation complexity by prohibiting the “±3” cases and support error-free training on GPU without accuracy loss originating from the mismatch between training and deployment. A PE is built based on this multiplier for parallel computation with 82% power reduction and 70% area reduction. Second, the proposed NMC-friendly data flow supports efficient data reuse and hence reduces off-chip memory traffic. The data flow supports data reuse of up to 16 times, matching the number of PEs and enabling regular read and write patterns. Third, a hardware-aware layer-wise model deployment approach is proposed with a memory space contiguity-aware (MSCA) model reshape strategy, and a hardware-aware NN splitting and scheduling algorithm. The proposed MSCA strategy maximizes burst access, and the proposed algorithm achieves efficient computation with high data reuse and low memory access. This deployment approach can achieve a reduction in memory access latency of 16.6%–32.0%. Measurements on a 22-nm test chip demonstrate a peak power efficiency of 33.98 TOPS/W under synthetic full-PE-utilization conditions, while achieving 12.92–29.11 TOPS/W for end-to-end NN inference on DarkNet19, VGG16, ViT-Tiny, and ResNet34.

Compute-in-memory (CIM) has emerged as a promising paradigm for accelerating neural networks (NNs), offering high parallelism and superior energy efficiency. To fully leverage the potential of CIM accelerators for deploying NNs, it is essential to carefully optimize their mapping dataflows, which determine how computations and data are scheduled across CIM resources over space and time. However, the diversity of CIM architectures, with their varying hardware parameters and mapping constraints, makes it challenging to develop a unified framework that efficiently optimizes dataflows across different CIM systems. Most existing CIM dataflow frameworks are tailored to a limited range of architectures or dataflow types, and often neglect CIM-specific features such as weight-update scheduling, which limits their effectiveness and generality. In this work, we propose TriCIM, a general dataflow optimization framework designed to adapt to diverse CIM architectures. We begin by introducing a CIM-capacity-aware formulation that classifies the CIM dataflow space into three distinct regions, model-stationary, layer-stationary, and tile-stationary, based on the available CIM capacity and the model size. For each dataflow region, we identify specific bottlenecks and propose tailored optimization strategies, including load balancing, layer grouping, weight-update scheduling, tiling, and inter-tile ordering, to address region-specific bottlenecks and enhance dataflow efficiency. Our evaluation across various CIM accelerators and representative NN models demonstrates that TriCIM consistently finds optimal dataflows, achieving $1.1\times $ to $13.2\times $ runtime speedup compared to state-of-the-art frameworks.

Multi-level-cell (MLC) resistive random-access memory (RRAM) promises superior computational density and energy efficiency for compute-in-memory (CIM) systems, yet its potential is limited by analog RRAM instability and the power-hungry bitline (BL) regulation amplifiers in prior Ohm’s-law-based designs. We demonstrate a 180-nm CIM macro with process-optimized back-end-of-line (BEOL) HfO₂ MLC RRAM. The devices exhibit stable 3-bit conductance states (74%. Silicon measurements of the 180-nm prototype deliver a peak energy (area) efficiency of 819 TOPS/W/bit (1.115 TOPS/mm²/bit). Furthermore, post-layout simulations of a 22-nm implementation project 14,123 TOPS/W/bit and 412.2 TOPS/mm²/bit, respectively.

There are two general approaches in guiding intelligent vision system development: one emphasizes ultra‐flexibility (reconfigurability) for adapting to various scenarios, and the other emphasizes ultrahigh power efficiency tailored to specific applications. The pinnacle design is geared toward the biological vision system with concurrent high levels of on‐demand intelligence, efficiency, and flexibility. However, current state‐of‐the‐art intelligent vision systems are far behind, relying on heterogeneously integrated and limited‐function single devices, alongside rigid sensing/computing architecture, thus preventing flexibility for low area and power efficiency toward dynamic and unpredictable scenarios. This work bridges the neuromorphic gap with an on‐demand ultra‐reconfigurable vision system, demonstrating true reconfigurability across device, cell, array and system levels. This is enabled by a multi‐paradigm device array capable of seamless switching between spiking, non‐spiking, neuromorphic imaging (NI), and artificial intelligence (AI) computing modes, as well as a reconfigurable circuit and architecture design. The system is capable of on‐demand allocating resources between NI and AI functionalities for high‐quality smart imaging and high‐accuracy recognition tasks, and transitioning between spiking and non‐spiking modes for frameless dynamic and frame‐based static scenarios. Superior power efficiencies of up to 52.6 TOPS/W for NI‐centric computing and 75.5 TOPS/W for NI/AI hybrid computing are achieved, which are up to two orders of magnitude larger than the state‐of‐the‐art intelligent vision system.