Jiamin Li
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Jiamin Li has a total of 79 co-authors. Here are the top co-authors by number of shared publications:
- Longyang Lin
Southern University of Science and Technology
10 shared publications - Yida Li
Southern University of Science and Technology
5 shared publications - Humiao Li
Southern University of Science and Technology
4 shared publications - Jerald Yoo
Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea
4 shared publications - Zhen Kong
Southern University of Science and Technology
4 shared publications - Zhengke Yang
Southern University of Science and Technology
4 shared publications
Latest Publications
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6000-6013
An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6000-6013
An Intelligent Vision SoC With Fully Analog Sensing-to-Inference Pipeline and Linearity-Recovery RRAM Compute-in-Memory
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 34 (11) , 3467-3477
A Posit-FP-Mixed FMA With Bitwidth-Adaptive Clocking and Accuracy-Throughput Optimization
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 34 (11) , 3467-3477
A Posit-FP-Mixed FMA With Bitwidth-Adaptive Clocking and Accuracy-Throughput Optimization
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6517-6530
Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 61 (11) , 6517-6530
Raisu: A Radiation-Tolerant Neuromorphic Imager With In-Pixel Self-Healing and Unified Spiking Processing for Spaceborne Vision
- 2 April 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (6) , 1109-1112
Stable On-Chip MLC RRAM With a Bitline Regulation-Free Analog MAC Scheme for High-Efficiency In-Memory Computing
Multi-level-cell (MLC) resistive random-access memory (RRAM) promises superior computational density and energy efficiency for compute-in-memory (CIM) systems, yet its potential is limited by analog RRAM instability and the power-hungry bitline (BL) regulation amplifiers in prior Ohm’s-law-based designs. We demonstrate a 180-nm CIM macro with process-optimized back-end-of-line (BEOL) HfO2 MLC RRAM. The devices exhibit stable 3-bit conductance states (74%. Silicon measurements of the 180-nm prototype deliver a peak energy (area) efficiency of 819 TOPS/W/bit (1.115 TOPS/mm2/bit). Furthermore, post-layout simulations of a 22-nm implementation project 14,123 TOPS/W/bit and 412.2 TOPS/mm2/bit, respectively.
- 2 April 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 47 (6) , 1109-1112
Stable On-Chip MLC RRAM With a Bitline Regulation-Free Analog MAC Scheme for High-Efficiency In-Memory Computing
Multi-level-cell (MLC) resistive random-access memory (RRAM) promises superior computational density and energy efficiency for compute-in-memory (CIM) systems, yet its potential is limited by analog RRAM instability and the power-hungry bitline (BL) regulation amplifiers in prior Ohm’s-law-based designs. We demonstrate a 180-nm CIM macro with process-optimized back-end-of-line (BEOL) HfO2 MLC RRAM. The devices exhibit stable 3-bit conductance states (74%. Silicon measurements of the 180-nm prototype deliver a peak energy (area) efficiency of 819 TOPS/W/bit (1.115 TOPS/mm2/bit). Furthermore, post-layout simulations of a 22-nm implementation project 14,123 TOPS/W/bit and 412.2 TOPS/mm2/bit, respectively.
- 28 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. PP (00189200) , 1-15
AdaPIM: A CIM-Based General-Purpose Vision Accelerator With Adaptive Inter-Macro Parallelism and Multi-Level Feature Reuse
Recent advances in computer vision (CV) have introduced a variety of neural network (NN) architectures, including convolutional neural networks (CNNs), vision Transformers, and hybrid CNN-Transformer models. These models involve operators with widely varying computation and memory access patterns, demanding highly flexible and adaptive hardware for efficient execution. However, prior vision accelerators typically adopt fixed, one-size-fits-all designs, leading to inefficient hardware utilization under such diversity. In this work, we propose AdaPIM, an adaptive compute-in-memory (CIM) accelerator that dynamically reconfigures hardware resources to match the varying computation and memory characteristics of diverse CV workloads. AdaPIM incorporates: 1) a reconfigurable 4D-CIM processor that enables adaptive inter-macro parallelism along four architectural dimensions to improve spatial utilization under diverse computation patterns; 2) a flexible on-chip memory system that supports adaptive feature reuse at both register and global buffer levels to reduce on-/off-chip memory traffic under varying access patterns; and 3) a high-throughput vector core optimized for Softmax and layer normalization (LN) through algorithm-architecture co-design. Fabricated in 22nm, AdaPIM achieves chip-level energy efficiency of 22.7–63.9TOPS/W and system-level latency [including external memory access (EMA)] of 1.87–17.16 ms/frame with hardware utilization up to 83.12%, delivering improvements of 1.09– $13.96\times $ in frame rate and 1.76– $3.41\times $ in utilization, respectively, over state-of-the-art accelerators across diverse vision workloads.
- 28 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. PP (00189200) , 1-15
AdaPIM: A CIM-Based General-Purpose Vision Accelerator With Adaptive Inter-Macro Parallelism and Multi-Level Feature Reuse
Recent advances in computer vision (CV) have introduced a variety of neural network (NN) architectures, including convolutional neural networks (CNNs), vision Transformers, and hybrid CNN-Transformer models. These models involve operators with widely varying computation and memory access patterns, demanding highly flexible and adaptive hardware for efficient execution. However, prior vision accelerators typically adopt fixed, one-size-fits-all designs, leading to inefficient hardware utilization under such diversity. In this work, we propose AdaPIM, an adaptive compute-in-memory (CIM) accelerator that dynamically reconfigures hardware resources to match the varying computation and memory characteristics of diverse CV workloads. AdaPIM incorporates: 1) a reconfigurable 4D-CIM processor that enables adaptive inter-macro parallelism along four architectural dimensions to improve spatial utilization under diverse computation patterns; 2) a flexible on-chip memory system that supports adaptive feature reuse at both register and global buffer levels to reduce on-/off-chip memory traffic under varying access patterns; and 3) a high-throughput vector core optimized for Softmax and layer normalization (LN) through algorithm-architecture co-design. Fabricated in 22nm, AdaPIM achieves chip-level energy efficiency of 22.7–63.9TOPS/W and system-level latency [including external memory access (EMA)] of 1.87–17.16 ms/frame with hardware utilization up to 83.12%, delivering improvements of 1.09– $13.96\times $ in frame rate and 1.76– $3.41\times $ in utilization, respectively, over state-of-the-art accelerators across diverse vision workloads.
- Open Access
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- p. 1-14
A 3-D Connectivity CMOS Ising Machine With 12-Way Toroidal Hexagonal Close-Packed Supply-and-Bulk Injection Locking Oscillators for Combinatorial Optimization
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- p. 1-14
Open AccessA 3-D Connectivity CMOS Ising Machine With 12-Way Toroidal Hexagonal Close-Packed Supply-and-Bulk Injection Locking Oscillators for Combinatorial Optimization
- Open Access
- 10 December 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of the Solid-State Circuits Society
- Vol. 5, 377-387
A 0.5 nJ/Conversion Self-Resetting Energy-Autonomous Multi-Node Temperature Sensor With Hybrid Energy Harvesting
This article presents an energy-autonomous, self-resetting, multi-node temperature sensor powered by hybrid energy harvesting. The ultra-low leakage Self-Adaptive Full Bridge Rectifier (SA-FBR) accepts any hybrid energy harvesting source at both sparse and abundant inputs and suppresses the leakage by 1000×. The Dynamic Power Management Unit (D-PMU) enables event-driven wake-up capability that allows for 97.3% power saving during standby mode. The 0.5 nJ/conversion temperature sensor in 0.18 μm CMOS uses active self-resetting, spike-based coding to achieve the widest measurement range of -10∘C to 110∘C to date.
- 10 December 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Open Journal of the Solid-State Circuits Society
- Vol. 5, 377-387
Open AccessA 0.5 nJ/Conversion Self-Resetting Energy-Autonomous Multi-Node Temperature Sensor With Hybrid Energy Harvesting
This article presents an energy-autonomous, self-resetting, multi-node temperature sensor powered by hybrid energy harvesting. The ultra-low leakage Self-Adaptive Full Bridge Rectifier (SA-FBR) accepts any hybrid energy harvesting source at both sparse and abundant inputs and suppresses the leakage by 1000×. The Dynamic Power Management Unit (D-PMU) enables event-driven wake-up capability that allows for 97.3% power saving during standby mode. The 0.5 nJ/conversion temperature sensor in 0.18 μm CMOS uses active self-resetting, spike-based coding to achieve the widest measurement range of -10∘C to 110∘C to date.
- 3 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 34 (2) , 519-529
A Low-Power Speech-Based Depression Recognition Processor With Hierarchical Local–Global Network
Depression is a critical public health concern characterized by underdiagnosis, often due to stigma, lack of awareness, and reluctance to seek help. Cases of delayed intervention could be alleviated by wearable solutions which enable continuous and unobtrusive monitoring of depression indicators. Compared to electroencephalogram (EEG)-based and video-based depression recognition, speech-based approaches can be performed without deliberate user attention. However, due to the limited accuracy of existing algorithms and constrained resources at edge, performing accurate speech-based depression recognition on wearable platforms remains a challenge. Therefore, to achieve unobtrusive, accurate, and efficient depression recognition at edge, this work presents a hierarchical local–global network (HLG-Net) and optimized processor design for speech-based depression recognition. The proposed HLG-Net integrates convolutional neural networks (CNNs) with multihead attention (MHA) mechanism to simultaneously capture local acoustic features and global utterance-level coherence, enhancing depression stage recognition. For efficient processor design, a cross-layer buffered dataflow is proposed for efficient data handling, reducing data storage by 98.77%. The computing unit (CU) employs layer fusion, operator optimization, and quantization techniques to further improve resource utilization and reduce power consumption while preserving recognition accuracy. System-level low-power techniques such as clock/input gating and near-threshold design for application specific integrated circuit (ASIC) further reduce power consumption. The proposed processor implemented on field-programmable gate array (FPGA) (XC7Z100-2FFG900) achieves the lowest reported mean absolute error (MAE) of 5.13 on AVEC 2014 database. The 180-nm ASIC implementation shows a simulated power consumption of $17.4~\mu $ W at 0.4 V. The results demonstrate the feasibility of accurate and efficient speech-based depression recognition on wearables.
- 3 November 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 34 (2) , 519-529
A Low-Power Speech-Based Depression Recognition Processor With Hierarchical Local–Global Network
Depression is a critical public health concern characterized by underdiagnosis, often due to stigma, lack of awareness, and reluctance to seek help. Cases of delayed intervention could be alleviated by wearable solutions which enable continuous and unobtrusive monitoring of depression indicators. Compared to electroencephalogram (EEG)-based and video-based depression recognition, speech-based approaches can be performed without deliberate user attention. However, due to the limited accuracy of existing algorithms and constrained resources at edge, performing accurate speech-based depression recognition on wearable platforms remains a challenge. Therefore, to achieve unobtrusive, accurate, and efficient depression recognition at edge, this work presents a hierarchical local–global network (HLG-Net) and optimized processor design for speech-based depression recognition. The proposed HLG-Net integrates convolutional neural networks (CNNs) with multihead attention (MHA) mechanism to simultaneously capture local acoustic features and global utterance-level coherence, enhancing depression stage recognition. For efficient processor design, a cross-layer buffered dataflow is proposed for efficient data handling, reducing data storage by 98.77%. The computing unit (CU) employs layer fusion, operator optimization, and quantization techniques to further improve resource utilization and reduce power consumption while preserving recognition accuracy. System-level low-power techniques such as clock/input gating and near-threshold design for application specific integrated circuit (ASIC) further reduce power consumption. The proposed processor implemented on field-programmable gate array (FPGA) (XC7Z100-2FFG900) achieves the lowest reported mean absolute error (MAE) of 5.13 on AVEC 2014 database. The 180-nm ASIC implementation shows a simulated power consumption of $17.4~\mu $ W at 0.4 V. The results demonstrate the feasibility of accurate and efficient speech-based depression recognition on wearables.
- 16 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 72 (11) , 1645-1649
A Leakage-Suppressing Differential-Drive Rectifier for Sporadic Wearable Triboelectric Energy Harvesting
This brief presents a leakage-suppressing differential-drive rectifier for triboelectric energy harvesting from sporadic human motions. Unlike triboelectric energy harvesting in the ambience (e.g., from wind, tide, mechanical motions) that allows for larger triboelectric nanogenerator (TENG) form factor and higher vibrational frequency, wearable triboelectric energy harvesting from human motions is area-constrained, sporadic and low-frequency. Such characteristics result in low power generation and low-frequency excitations with long inactive period, challenging the harvester interface circuit design. In this work, a leakage-suppressing differential-drive rectifier is proposed, which enables the reduction of reverse leakage of differential-drive rectifier by 5 orders of magnitude during the inactive period, while improving the power conversion efficiency (PCE) during the harvesting period. The passive structure does not incur additional power overhead, making it suitable for nW-level power scavenging. Fabricated in 40 nm CMOS, the proposed rectifier achieves a maximum PCE of 91.8 Hz and nW-level TENG power harvested from body motions.
- 16 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 72 (11) , 1645-1649
A Leakage-Suppressing Differential-Drive Rectifier for Sporadic Wearable Triboelectric Energy Harvesting
This brief presents a leakage-suppressing differential-drive rectifier for triboelectric energy harvesting from sporadic human motions. Unlike triboelectric energy harvesting in the ambience (e.g., from wind, tide, mechanical motions) that allows for larger triboelectric nanogenerator (TENG) form factor and higher vibrational frequency, wearable triboelectric energy harvesting from human motions is area-constrained, sporadic and low-frequency. Such characteristics result in low power generation and low-frequency excitations with long inactive period, challenging the harvester interface circuit design. In this work, a leakage-suppressing differential-drive rectifier is proposed, which enables the reduction of reverse leakage of differential-drive rectifier by 5 orders of magnitude during the inactive period, while improving the power conversion efficiency (PCE) during the harvesting period. The passive structure does not incur additional power overhead, making it suitable for nW-level power scavenging. Fabricated in 40 nm CMOS, the proposed rectifier achieves a maximum PCE of 91.8 Hz and nW-level TENG power harvested from body motions.