Saurabh Jain

This work introduces the ±CIM SRAM macro having the unique capability of performing in-memory multiply-and-accumulate computation with signed inputs and signed weights. This uniquely enables the execution of a broad set of workloads, ranging from storage, subsequent signal processing, and pre-conditioning or feature extraction to final convolutional neural network (CNN) computations. The ability to handle arbitrary input/weight sign in any operand within the same array and the same access cycle enables true end-to-end data locality, preserving the inherent benefits of in-memory computing along the entire signal chain. The proposed broad-purpose computing SRAM is based on a commercial 8T dual-port bitcell, and its simplicity allows the enhanced periphery to be pitch-matched with the array, making it amenable for automated design via memory compilers. The ±CIM pipelined architecture allows concurrent read/write and compute operations, avoiding the traditional memory unavailability in compute mode for improved throughput and easier system integration. A 40-nm test chip demonstrating the ±CIM architecture with adjustable input/weight precision exhibits an energy efficiency up to 41 TOPS/W, at an area (energy) overhead of 38% (25%) and negligible performance overhead compared to a compiled SRAM baseline. The sub-LSB computation mean-squared error associated with mismatch (0.38 LSB) and temporal noise (0.62 LSB) confirms the inherent robustness of the architecture. When used for neural network tasks (LeNet-5 and VGG), the accuracy drop is kept between 0.3% and 3.4%, compared to a double-precision software implementation. As an example of digital signal processing (DSP) workload, a frequency-domain feature extractor for voice activity detection keeps the accuracy drop lower than 3.8%.

When making an online purchase, it becomes important for the customer to read the product reviews carefully and make a decision based on that. However, reviews can be lengthy, may contain repeated, or sometimes irrelevant information that does not help in decision making. In this paper, we introduce MRCBert, a novel unsupervised method to generate summaries from product reviews. We leverage Machine Reading Comprehension, i.e. MRC, approach to extract relevant opinions and generate both rating-wise and aspect-wise summaries from reviews. Through MRCBert we show that we can obtain reasonable performance using existing models and transfer learning, which can be useful for learning under limited or low resource scenarios. We demonstrated our results on reviews of a product from the Electronics category in the Amazon Reviews dataset. Our approach is unsupervised as it does not require any domain-specific dataset, such as the product review dataset, for training or fine-tuning. Instead, we have used SQuAD v1.1 dataset only to fine-tune BERT for the MRC task. Since MRCBert does not require a task-specific dataset, it can be easily adapted and used in other domains.

In this article, a battery-indifferent microcontroller unit (MCU) with wide power-performance scaling is presented to enable continuous operation with a sub-mm² on-chip solar cell, even when the battery runs out of energy. The MCU is based on dual-mode standard cells to extend power-performance flexibility well beyond allowed by voltage-scaled CMOS logic. Ripple power gating is introduced to allow the processor to boot under scarce light intensity and no battery energy. The dual-mode logic is experimentally characterized at the gate level, analyzing the underlying tradeoffs among power, energy, delay, and noise margin. Compared with voltage-scaled CMOS logic, dual-mode logic is shown to reduce the minimum power/gate by 750x to enable purely harvested operation while having comparable energy/gate to prolong battery-powered operation. The proposed ripple power gating self-startup technique enables MSP430-compatible MCU cold start with an on-chip 0.54-mm² solar cell at a dim 55-lx light condition.

In this paper, a broad-purpose compute-inmemory solution (±CIM) able to handle arbitrary sign in both inputs/features and weights/coefficients is introduced. The ability to operate on arbitrary sign and under variable precision on both operands enables a wide range of applications, ranging from conventional neural networks to digital signal processing and monitoring. The ±CIM pipelined architecture, the reconfigurable row encoder and the adoption of a commercial 2-port bitcell allow uninterrupted memory availability for conventional read/write, even when performing in-memory computations. A 40nm testchip shows the ability of the ±CIM architecture to perform both neural network computations and classical signal processing. At 6-bit precision, the measured worst-case mismatch (noise) is 0.38 (0.62) LSB. The achieved accuracy when executing a LeNet-5 neural net workload is 98.3%, which is within 1.3 state-of-the-art software implementations. As example of signal processing workload, 91.7% accuracy is achieved in voice activity detection, which is within 2.8% of a software implementation. Overall, the energy efficiency (throughput) of 41 TOPS/W (122 GOPS) is achieved at 38% area overhead, over a conventional SRAM with the same 4-KB capacity.

This work introduces reconfiguration for energy-performance adaptation beyond conventional voltage scaling in microcontroller-based systems. Coordinated thread-level processor and row-level memory reconfiguration are enabled by an architecture-agnostic methodology. The latter requires low design and integration effort while reusing existing macros, including third-party intellectual properties (IPs) in an obfuscated or encrypted form. The methodology represents a drop-in solution that is applicable to extend the energy-performance tradeoff in existing designs. The proposed approach was demonstrated with a testchip implementing an ARM Cortex-M0 processor with 16-KB SRAM in 40 nm. The system demonstrates 1.8X throughput boost at nominal voltage (1.1 V) and 1.3X energy reduction at the minimum energy point (0.51 V) compared to voltage scaling with no reconfiguration. Such energy-performance range extension is achieved at 10.3% area overhead, which is mostly due to processor reconfiguration. Overall, the proposed approach reduces energy in the common case and increases performance when demanded, surpassing the capabilities of conventional voltage scaling, while reusing existing IPs and retaining the original software stack.

This article presents a power management unit (PMU) enabling ultra-wide power-performance tradeoff well beyond voltage scaling, and adaptation to the sensed power/energy availability in the harvester and battery. Gap-less power scaling by more than five orders of magnitude and down to nW permits continuous microcontroller unit (MCU) operation regardless of the battery energy availability, thanks to a sub-mm² on-chip harvester. Such battery-indifferent operation allows to considerably shrink the battery down, as battery discharge no longer has disruptive impact on operation. Battery-indifferent operation is enabled by introducing a purely harvested power mode in the PMU, and widely power-scalable circuits in critical blocks to maintain the power efficiency nearly constant down to nW level. To avoid pessimistic power/timing overdesign, a novel self-biasing comparator and a zero current switching scheme with fast convergence and circuit sharing across power modes are proposed. A 180-nm testchip shows MSP430-like MCU power scaling from sub-mW down to 1.85 nW, with at least 27x power dynamic range extension compared to prior art. Self-start-up from 2-nW harvested power is demonstrated, corresponding to a 0.8-mm² on-chip solar cell with 100-lx illuminance (i.e., equivalent to a very dark overcast day).

This paper introduces dynamically adaptable pipelines to enable microarchitecture-driven voltage scaling, adapting the microarchitecture to the most energy-efficient configuration for a time-varying throughput target or supply voltage requirement VDD. Dynamic adaptation of the pipeline depth is introduced to curtail the contribution that dominates the overall energy (e.g., dynamic, clock, and leakage), as dictated by the throughput target and VDD. Microarchitectural adaptation of the pipeline depth also flattens the energy dependence on VDD around the minimum-energy point, thus facilitating nearly minimum-energy operation in the presence of inaccuracies in VDD (e.g., discretization and non-idealities). Dynamically adaptable pipelines can be fully integrated with automated digital flows at design time and with dynamic voltage scaling schemes at run time. The proposed approach is demonstrated with a 256-point radix-4 fixed-point FFT engine on a 40-nm test chip. Measurements show energy savings up to 30% (38%) at iso-throughput (iso-voltage) in an area and the maximum performance penalty of 5% and 11%, respectively.

This paper introduces a transregional energy model to estimate the energy consumption of digital designs for voltages widely ranging from nominal down to deep sub-threshold. The model also predicts the optimal voltage at which the minimum energy point (MEP) occurs, and the resulting minimum energy achievable under aggressive voltage scaling. The model provides the energy profile versus voltage based on a few technology-dependent parameters that are extracted through simple circuit simulations, and other few design-dependent parameters extracted from synthesis or Place&Route reports at nominal voltage only. The model captures the effect of input-dependent (e.g., switching activity), technology-dependent (e.g., corner, transistor flavor), and micro-architectural parameters (e.g., logic depth). The model exhibits a typical error below 10%, and is well suited for design exploration under wide voltage scaling, as it avoids detailed and time-consuming multi-corner and multi-voltage iterations. Also, the model provides a quick estimate of the achievable MEP for a given design. Accordingly, the proposed model is a useful tool that supports early selection of the most energy-efficient design options to meet a targeted energy profile at low voltages.