Guillaume Renaud
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Research Interests
Guillaume Renaud has a total of 7 co-authors. Here are the top co-authors by number of shared publications:
- Farjad Shadmehri
Concordia University
1 shared publication Mamadou Diallo
TIMA Laboratory, CNRS, Grenoble INP, Université Grenoble Alpes, 38000 Grenoble, France
1 shared publication- Manuel J. Barragan
TIMA Laboratory, University of Grenoble Alpes, Grenoble, France
1 shared publication Marc Palardy-Sim
National Research Council Canada, Ottawa, Ontario, Canada
1 shared publicationMichael Jakubinek
National Research Council Canada, Ottawa, Ontario, Canada
1 shared publicationRebecca Rajs
Department of Mechanical, Industrial and Aerospace Engineering, Concordia University, Montreal, Quebec, CANADA
1 shared publication
Latest Publications
- Open Access
- 1 September 2020
- Published by Robertson Library, University of Prince Edward Island
Experimental Testing, Modeling, and Simulation of 3D Printed Composite Material for Morphing Wing Application
- 1 September 2020
- Published by Robertson Library, University of Prince Edward Island
Open AccessExperimental Testing, Modeling, and Simulation of 3D Printed Composite Material for Morphing Wing Application
- 9 November 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 27 (2) , 281-293
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs
This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.
- 9 November 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 27 (2) , 281-293
Fully Differential 4-V Output Range 14.5-ENOB Stepwise Ramp Stimulus Generator for On-Chip Static Linearity Test of ADCs
This paper presents an on-chip stepwise ramp stimulus generator aimed at static linearity test applications for analog-to-digital converters (ADCs). The proposed ramp stimulus generator is based on a simple switched-capacitor integrator with a constant dc input. The integrator has been conveniently modified to produce a very small integration gain proportional to the capacitance difference of two capacitors, in such a way that the resulting stepwise ramp signal at the output has a step size below the least significant bit (LSB) of the target ADC under test. In order to verify the feasibility of the proposed ramp generation technique, this paper details the design and experimental characterization of a proof-of-concept stepwise ramp generator in a 65-nm CMOS technology. Experimental results on 15 fabricated samples show an average linearity of 14.5 effective bits in a differential output range of ±2 V. Moreover, a discrete-time static linearity measurement strategy is proposed and, as a proof-of-concept validation, it is verified on an off-the-shelf 11-bit ADC using the fabricated generator samples. Experimental results show an accuracy of ±0.3 LSB in the measurement of the integral nonlinearity of the ADC under test.