Cheng Li

A new four-frequency-shift keying (4FSK) transceiver (TRX) at 145–185-GHz operation frequency is presented. The proposed non-coherent TRX is a fully integrated bit-in–bit-out communication system without the need for separate modulators/demodulators (modems). The transmitter (TX) core includes only one voltage-controlled oscillator (VCO), which can generate four different frequencies based on the two parallel streams of binary data at its input. The receiver (RX) with a frequency overlapping architecture demodulates the 4FSK signal and recovers the two parallel streams of binary data. Both the TX and the RX are designed and fabricated in a standard 65-nm CMOS process. The TX and RX consume 62-and 120-mW power, respectively. The highest achieved data rate is 17 Gb/s at an 18-cm link distance with 10.7-pJ/bit energy efficiency.

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step.

This paper reports a calibration scheme that can be used to correct the inter-stage gain error in two-stage analog-to-digital converters (ADCs). We measure the static nonlinearity at the raw ADC outputs and compensate it through a feedback path to adjust the gain in the analog domain, which avoids the dynamic range loss in the conventional pure digital calibrations. The proposed scheme detects the error via the missing-code-occurrence probability (MCOP), which is insensitive to the comparator offset and has better immunity to its noise. Besides the gain error, we discuss other DAC linearity issues, such as the implementations of the reference buffer and the low-dropout (LDO) regulator. To verify the MCOP calibration, we design a 12-bit successive-approximation-register ADC, employing the bridge-DAC, in 65-nm CMOS. We integrate the ADC operating at 100 MS/s with the MCOP calibration, the reference buffers, and the LDO. The measurement results demonstrate the linearity enhancement after the proposed calibration, where we improve the signal-to-noise-and-distortion ratio to 61.38 dB, leading to a FoM of 16.7 fJ/conversion step at the Nyquist input frequency.

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results.

This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large differential nonlinearity and missing codes, eventually degrading conversion accuracy. The calibration concept aims to differentiate the error outputs and correct them by simply performing a subtraction in the digital domain. It runs in the background with a little hardware overhead, and does not depend on the type of the input signal or reduce the dynamic range. Two prototypes were measured which are made up of different reference generation circuits. Design #1 has the reference voltage from off-chip and a 3-pF decoupling capacitor on-chip, while design #2 includes an on-chip reference buffer. Both designs were fabricated in 65-nm CMOS and achieve at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) after calibration. The total core area is around 0.012 mm ² for both chips and the Nyquist SNDR of designs #1 and #2 is 59.03 and 57.93 dB, respectively.

High quality fully integrated power supplies could notably improve the performances of the noise‐sensitive building block in the UWB communication systems. Double buffers are inserted into the cascode flipped‐voltage‐follower (FVF) topology to enable designing the dominant pole at the output node for better power supply rejection (PSR) and less voltage variation during load transient. An enhanced super source follower (E‐SSF) is proposed to further reduce the output impedance of the buffer that drives the power transistor. The FVF‐based low dropout regulator (LDO) with E‐SSF achieves a worst‐case PSR of −18.9 dB across the full spectrum and a transient response time of 312 ps. The proposed LDO is designed in a 28 nm CMOS process and consumes 100 μA quiescent current with 1.0 V input and 0.8 V output voltages. In total, 120 pF on‐chip capacitors are used for filtering.