Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC
- 17 August 2018
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 66 (1) , 82-93
Abstract
The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results.Keywords
Funding Information
- Universidade de Macau (MYRG2018-00104-AMSV)
- Fundo para o Desenvolvimento das Ciências e da Tecnologia (117/2016/A3)
This publication has 17 references indexed in Scilit:
- A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS2017
- A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS2016
- A 12-bit 104 MS/s SAR ADC in 28 nm CMOS for Digitally-Assisted Wireless TransmittersIEEE Journal of Solid-State Circuits, 2016
- Metastablility in SAR ADCsIEEE Transactions on Circuits and Systems II: Express Briefs, 2016
- Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOSIEEE Journal of Solid-State Circuits, 2016
- Miller's Theorem [Circuit Intuitions]IEEE Solid-State Circuits Magazine, 2015
- Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCsIEEE Transactions on Circuits and Systems I: Regular Papers, 2015
- A 0.003 mm$^{2}$ 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed SwitchingIEEE Journal of Solid-State Circuits, 2015
- Analysis of Metastability in Pipelined ADCsIEEE Journal of Solid-State Circuits, 2014
- A 550-$\mu\hbox{W}$ 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error CorrectionIEEE Journal of Solid-State Circuits, 2011