Joris Lambrecht

We present a 7-bit wireline digital-to-analog converter (DAC), fabricated in 5-nm FinFET CMOS. The number of source-series terminated (SST) cells in the output stage is reduced to 34 by employing cells with relative weight 1 and 4. Each differential cell integrates two single-ended three-stage 8:1 return-to-zero (RZ) multiplexers with an integrated SST driver and a clock pulse generator (CPG), which generates the required clock pulses for the multiplexers from an eight-phase clocking scheme. The clock buffers driving these cells feature shunt inductors to reduce power consumption and jitter. At 150 GSa/s, the effective number of bits (ENOB) was measured to be 4.1 b for a 72.8-GHz sinewave. The DAC consumes 621 mW from a 0.9- and 0.96-V supply. Eye diagrams of 150-GBd NRZ, PAM-4, and PAM-6 are demonstrated, pre-equalized using a 10-tap feedforward equalizer.

This letter presents a 106.25 Gb/s two amplitude-shift keying differential binary phase-shift keying (2ASK-DBPSK) co-integrated self-coherent optical receiver consisting of a silicon photonic integrated circuit (PIC) and an electrical integrated circuit (EIC). The optical receiver detects the phase information of the optical signal using a delay line interferometer (DLI) on the PIC. Without any equalization, a sensitivity of -7.3 dBm at a bit-error rate (BER) of $\mathbf {3.8\times 10^{-3}}$ was measured. Using a 9-tap feed-forward equalizer (FFE, implemented offline) a sensitivity of -7.2 dBm at a BER of $\mathbf {2.4\times 10^{-4}}$ was measured. Unlike 4-level pulse amplitude modulation (PAM-4), the approach does not necessarily need linear electronics. In addition, no local oscillator laser is required at the receiver to detect the optical phase information.

This paper presents an analog demultiplexing optical receiver capable of converting a high-baudrate optical input into two half-rate output signals, facilitating the use of lower-speed analog-to-digital converters (ADCs). This architecture not only simplifies the ADC design but also offers scalability for future high-speed receiver systems. The receiver integrates a germanium photodetector on a silicon photonic integrated circuit (PIC), a silicon germanium (SiGe) traveling-wave transimpedance amplifier (TIA), and a 4-way interleaved 256-GS/s SiGe analog demultiplexer (ADEMUX) operating in 1-to-2 mode. In order to evaluate the performance of this receiver, O-band transmission experiments were conducted at symbol rates ranging from 100 to 128 GBd for both non-return to zero (NRZ) and pulse-amplitude modulation 4-level (PAM4) modulation formats over fiber lengths up to 50 km without receiver-side digital signal processing (DSP).

An integrated balanced quasi-coherent receiver front end for 50G Passive Optical Network (PON) was designed and experimentally demonstrated. The received intensity modulated optical signal is boosted by a local oscillator (LO) laser and downconverted to an electrical intermediate frequency (IF) signal after integrated 2×2 multi-mode interference (MMI) and high-speed germanium photodiode (PD). By adjusting the wavelength offset between LO and transmitter laser, the IF can be chosen near the 3 dB bandwidth of RX front end to suppress the chromatic dispersion (CD) induced distortion in the upper sideband. After amplification by an integrated transimpedance amplifier (TIA), the baseband signal is demodulated via a simple square and low-pass-filter (LPF) function using offline digital signal processing (DSP). In contrast to traditional coherent receivers, no phase locking or carrier phase recovery is required. For 50 Gb/s non-return to zero(NRZ), corresponding to pre-FEC limit at bit error rate (BER) reference level 1e-2 in ITU-T G.9804, the measured optical modulated amplitude (OMA) sensitivity is −25.8 dBm (average received optical power is $-27$ dBm) in back-to-back (B2B) case and $-19.8$ dBm after 5 km standard single-mode-fiber (SSMF) transmission in C-band at 1550 nm, without any CD compensation and equalization in DSP. Measurement results show that total chromatic dispersion of 85 ps/nm can be handled for BER value lower than 1e-2. Compared with direct detection by using the same integrated high-speed germanium photodiode and TIA, the measured OMA sensitivity at BER reference level 1e-2 of the proposed quasi-coherent receiver has 13 dB improvement in B2B case and higher than 16 dB enhancement after 5 km SSMF transmission in C-band for 50 Gb/s NRZ with 10.1 dBm LO power. By reducing LO power for high-power input signals, $>$24 dB dynamic range is covered at BER reference level 1e-2, which satisfies class C+ level in ITU-T 50G PON PMD layer specification, assuming 8.5 dBm transmitter launch power.

The recent proliferation of artificial intelligence and machine learning applications relying on large language models is fueling unprecedented demand for compute capacity. Associated with this is a need to scale capacities of short-reach optical transceivers towards multiplex Terabit/s, while maintaining integration density (frontpanel or beachfront density) and energy efficiency (pJ/bit). One option to scale transceiver capacity is to increase the bandwidth per lane from today's 200G to 400G or even higher: coherent transceiver technology is then expected to play an ever more important role. Photonics and electronics with higher bandwidths beyond 100GHz will play a crucial role. Integration of thin-film LiNbO3 modulator onto a Silicon Photonics platform is shown to be a viable option to meet the needs for new generations of optical transceivers. Front-end electronics such as linear modulator drivers and transimpedance amplifiers can rely on traveling-wave design approaches to allow continued bandwidth scaling despite (relative) slowing transistor speeds. Novel wireline data converter architectures can be used to overcome limitations of existing implementations. Maintaining signal integrity from photonics and electronics can be facilitated using both 2.5D and 3D integration approaches. While the introduction of novel materials and architectures will require time to further mature, optical transceivers operating at baudrates up to and beyond 200Gbaud are now just beyond the horizon.

We present an optical receiver using a SiGe BiCMOS transimpedance amplifier (TIA) chip with a 3 dB bandwidth over 67 GHz and a transimpedance gain up to 77 dB$\Omega$. This TIA consists of a single-ended input stage and two differential gain stages followed by a differential output stage. These traveling-wave stages feature variable gain and peaking. A TIA channel consumes 487.5 mW, or 2.2 pJ/bit operating at 112 GBd PAM-4, and occupies a chip area of 1.125 mm². The THD at 1 GHz (10 GHz) is kept below 2% (5%) for input swings up to 1.6 mApp (1.3 mApp) by reducing the gain. After wire bonding the input of this TIA to a silicon photonic germanium photodiode, a bandwidth of 64 GHz and a group delay variation of 20.3 ps are obtained. Using a 10-tap feedforward equalizer (FFE), opto-electrical eye diagrams are captured and for 128 GBd NRZ, a sensitivity of -5.9 dBm is measured at a bit error rate (BER) of 1E-12. For 112 GBd PAM4, the KP4 sensitivity level is -4.8 dBm. The input-referred noise is measured at 18.8 pA/$\sqrt{}$Hz.

This paper presents a 160 Gb/s four-level pulse-amplitude modulation (PAM-4) optical receiver based on a 130nm SiGe BiCMOS ( $\mathbf {f_{T}/f_{MAX} = 350/450}$ $\mathbf {GHz}$ ) fully differential transimpedance amplifier (TIA) and two silicon photonic Ge photodiodes (PDs). The high-speed path of the TIA consists of a TIA input stage (TIS) followed by two variable gain amplifiers (VGAs) and an output buffer. A novel fully differential input DC current cancellation (IDCC) circuit is proposed to absorb the input DC currents and eliminate the DC offset of the TIS. 80 GBd PAM-4 operation is demonstrated with an off-line 5-tap feed-forward equalizer (FFE), achieving -7 dBm in-waveguide optical modulation amplitude (OMA) sensitivity at KP4-FEC ( $\mathbf {2.4\times 10^{-4}}$ ) and 0.99 pJ/b power consumption. 56, 64, and 72 GBd PAM-4 operations are demonstrated without any equalization, achieving -9.2, -8.4, and -5.9 dBm OMA sensitivity at KP4-FEC, respectively. To the best of our knowledge, this integrated optical receiver achieves the best sensitivity at KP4-FEC and the lowest power consumption for 64, 72 and 80 GBd PAM-4 operations.

The surge of data traffic in emerging optical communication applications has led to the development of ultra-fast transceivers with extremely high data throughput. The latest transmitters and receivers aim for symbol rates of 150–200 Gbaud or even higher, striving to achieve bandwidths beyond 70 GHz. However, the current state-of-the-art analog-to-digital converters (ADCs) in advanced CMOS-FinFET technologies can only handle limited analog input bandwidths and sampling rates, becoming a bottleneck in enhancing the overall speed of the transceiver. A time-interleaved sampling front-end acting as an input signal de-interleaver can reduce the sub-ADCs’ analog bandwidth and clock jitter requirements. This article investigates a current-mode time-interleaved 1–4 sampling front-end operating at 200–256 GS/s, using a 50% duty-cycle slew-rate insensitive quadrature clocking strategy. The chip was fabricated in a 130-nm SiGe BiCMOS technology and was characterized by single-tone sinusoidal and non-return-to-zero/pulse-amplitude-modulation-4-level (NRZ/PAM-4) measurements at 200, 224, and 256 GS/s. The chip demonstrates a 3-dB analog input bandwidth beyond 67 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 27.8–34.1 dB (at 200 GS/s), 25–36.3 dB (at 224 GS/s), and 22.3–39 dB (at 256 GS/s) for input frequencies from 1.1 to 67.1 GHz. The analog demultiplexing functionality of the sampling front-end is demonstrated with 100, 112, and 128 Gbaud NRZ/PAM-4 measurements. The complete chip consumes a power of 1.1 W at 256 GS/s, corresponding to an efficiency of 4.3 pJ/sample or 4.3 pJ/bit (with two samples per symbol).

This paper introduces an opto-electronic and opto-electronic-opto circuit capable of generating a Sigmoid shaped non-linear activation function (NLAF) for photonic neural networks. The main element of the circuit is a III-V photonic integrated circuit featuring an O-band semiconductor optical amplifier (SOA) co-integrated with a uni-travelling carrier photodiode, connected to a Bi-CMOS transimpedance amplifier (TIA). Experimental results from two 10 GHz 32-level mirrored step-wise pulse sequences, and three 30-level random peak power pulse sequences, validate the proposed concept, showcasing the variation of the achieved sigmoid NLAF from nearly stepwise to linear by appropriately varying the SOA current, injection of an external CW signal and proper configuration of the TIA settings.