A 200–256-GS/s Current-Mode 4-Way Interleaved Sampling Front-End With Over 67-GHz Bandwidth Using a Slew-Rate Insensitive Clocking Scheme
- 2 July 2024
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 60 (1) , 244-259
Abstract
The surge of data traffic in emerging optical communication applications has led to the development of ultra-fast transceivers with extremely high data throughput. The latest transmitters and receivers aim for symbol rates of 150–200 Gbaud or even higher, striving to achieve bandwidths beyond 70 GHz. However, the current state-of-the-art analog-to-digital converters (ADCs) in advanced CMOS-FinFET technologies can only handle limited analog input bandwidths and sampling rates, becoming a bottleneck in enhancing the overall speed of the transceiver. A time-interleaved sampling front-end acting as an input signal de-interleaver can reduce the sub-ADCs’ analog bandwidth and clock jitter requirements. This article investigates a current-mode time-interleaved 1–4 sampling front-end operating at 200–256 GS/s, using a 50% duty-cycle slew-rate insensitive quadrature clocking strategy. The chip was fabricated in a 130-nm SiGe BiCMOS technology and was characterized by single-tone sinusoidal and non-return-to-zero/pulse-amplitude-modulation-4-level (NRZ/PAM-4) measurements at 200, 224, and 256 GS/s. The chip demonstrates a 3-dB analog input bandwidth beyond 67 GHz and a signal-to-noise-and-distortion ratio (SNDR) of 27.8–34.1 dB (at 200 GS/s), 25–36.3 dB (at 224 GS/s), and 22.3–39 dB (at 256 GS/s) for input frequencies from 1.1 to 67.1 GHz. The analog demultiplexing functionality of the sampling front-end is demonstrated with 100, 112, and 128 Gbaud NRZ/PAM-4 measurements. The complete chip consumes a power of 1.1 W at 256 GS/s, corresponding to an efficiency of 4.3 pJ/sample or 4.3 pJ/bit (with two samples per symbol).Keywords
Funding Information
- imec High-Speed Transceiver and Coherent Transceiver Programs, European Union (EU)-Funded H2020 Projects POETICS (871769)
- Special Research Fund (BOF) of Ghent University
- Research Foundation Flanders
This publication has 29 references indexed in Scilit:
- A Shunt-Feedback TIA with Common-Base Variable Gain Input Stage for 128-GBaud Coherent Communication2023
- Time-Interleaved Switched Emitter Followers to Extend Front-End Sampling Rates to up to 200 GS/sIEEE Journal of Solid-State Circuits, 2022
- Track and Hold Amplifier Investigation for 100-GHz Bandwidth, 200-GS/s ADC Front EndsIEEE Solid-State Circuits Letters, 2022
- 200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator2021
- 1-to-4 Analog Demultiplexer With up to 128 GS/s for Interleaving of Bandwidth-Limited Digitizers in Wireline and Optical ReceiversIEEE Journal of Solid-State Circuits, 2021
- 64-GS/s 6-Bit Track-and-Hold Circuit with More Than 61 GHz Bandwidth at 1.0 Vpp Input Voltage Swing in 90-nm SiGe BiCMOS Technology2021
- 8.6 A Highly Reconfigurable 40-97GS/s DAC and ADC with 40GHz AFE Bandwidth and Sub-35fJ/conv-step for 400Gb/s Coherent Optical Applications in 7nm FinFET2021
- 8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-22021
- A 112-Gb/s PAM-4 Long-Reach Wireline Transceiver Using a 36-Way Time-Interleaved SAR ADC and Inverter-Based RX Analog Front-End in 7-nm FinFETIEEE Journal of Solid-State Circuits, 2020
- Compact Modeling of Proximity Effect in High- ${Q}$ Tapered Spiral InductorsIEEE Electron Device Letters, 2018