Karsten Hansen

CERN's strategic R&D programme on technologies for future experiments recently started investigating the TPSCo 65nm ISC CMOS imaging process for monolithic active pixels sensors for application in high energy physics. In collaboration with the ALICE experiment and other institutes, several prototypes demonstrated excellent performance, qualifying the technology. The Hybrid-to-Monolithic (H2M), a new test-chip produced in the same process but with a larger pixel pitch than previous prototypes, exhibits an unexpected asymmetric efficiency pattern. This contribution describes a simulation procedure combining TCAD, Monte Carlo and circuit simulations to model and understand this effect. It proved able to reproduce measurement results and attribute the asymmetric efficiency drop to a slow charge collection due to low amplitude potential wells created by the circuit layout and impacting efficiency via ballistic deficit.

The high energy physics community recently gained access to the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a higher in-pixel logic density in monolithic active pixel sensors (MAPS) compared to processes with larger feature sizes. To explore this novel technology, the Hybrid-to-Monolithic (H2M) test chip has been designed and manufactured. The design follows a digital-on-top design workflow and ports a hybrid pixel-detector architecture, with digital pulse processing in each pixel, into a monolithic chip. The chip matrix consists of 64×16 square pixels with a size of 35×35 μm², and a total active area of approximately 1.25 mm². The chip is operated and read out using the Caribou DAQ system. The measured threshold dispersion and noise agree with the expectation from front-end simulations. However, a non-uniform in-pixel response related to the size and location of the n-wells in the analog circuitry has been observed in test beam measurements and will be discussed in this contribution. This asymmetry in the pixel response, enhanced by the 35 μm pixel pitch — larger than in other prototypes — and certain features of the readout circuit, has not been observed in prototypes with smaller pixel pitches in this technology.

The DESY digital silicon photomultiplier (dSiPM) is a monolithic detector based on complementary metal-oxide-semiconductor (CMOS) single-photon avalanche diodes (SPADs) and features a fully digital readout. The dSiPM prototype was characterized using a picosecond injection laser. Different contributions to the time resolution from both SPADs and digitization electronics are quantified. The dSiPM achieves a temporal resolution of approximately 50 ps under optimal conditions, while localized charge deposition with the laser revealed in-pixel variations of the time resolution linked to the SPAD layout. Combining fast timing with a pixelated readout, the device is a promising candidate for 4D-tracking detectors and other precision timing applications.

Femtosecond transient soft X-ray absorption spectroscopy (XAS) is a very promising technique that can be employed at X-ray free-electron lasers (FELs) to investigate out-of-equilibrium dynamics for material and energy research. Here, a dedicated setup for soft X-rays available at the Spectroscopy and Coherent Scattering (SCS) instrument at the European X-ray Free-Electron Laser (European XFEL) is presented. It consists of a beam-splitting off-axis zone plate (BOZ) used in transmission to create three copies of the incoming beam, which are used to measure the transmitted intensity through the excited and unexcited sample, as well as to monitor the incoming intensity. Since these three intensity signals are detected shot by shot and simultaneously, this setup allows normalized shot-by-shot analysis of the transmission. For photon detection, an imaging detector capable of recording up to 800 images at 4.5 MHz frame rate during the FEL burst is employed, and allows a photon-shot-noise-limited sensitivity to be approached. The setup and its capabilities are reviewed as well as the online and offline analysis tools provided to users.

Flip-chip bonding is a key packaging technology to achieve the smallest form factor possible. Using copper as a direct under-bump metal and performing bonding under little force and at a low temperature eliminates the processing step for the deposition of a suitable wetting metal and offers an economical solution for electronic chip packaging. In this paper, various samples with copper and nickel–gold surface finishes are used to apply an in-house solder bumping, flip-chip bonding and reflow process to exhibit the bump-bond feasibility. Native oxides are reduced using process gases, and copper surface protection and solder wetting are achieved using copper formate. Lead-free 40 µm solder balls were bumped on 80 µm copper pads and 120 µm copper pillars to demonstrate a full intermetallic Cu–Cu bond as a base study for stacking applications. Using a low-force bonding technique, various chips with different dimensions were bonded at 0.5–16 MPa, followed by a reflow step at a maximum temperature of 270 °C. Then, 30 µm solder balls are utilized to bump the samples with NiAu and Cu bond pads at 50 µm pitch. A mean shear strength of 44 MPa was obtained for the 30 µm Cu samples. To the best of our knowledge, 30 µm solder bumping directly on the copper pads by producing copper formate is a novel research contribution.