Leonardus Cornelis Nicolaas de Vreede

Power amplifier (PA) performance in cellular base stations decreases significantly under antenna impedance variations. Conventional protection techniques, which use circulators or impedance-sensing circuitry, typically increase power consumption and system complexity, with limited scalability in massive-MIMO systems. This paper presents a hardware-efficient approach that estimates load impedance directly from measured PA I/Q data using deep learning, thereby eliminating the use of additional sensing hardware. Grounded in the coupling between load impedance and large-signal transistor dynamics, the method is motivated by the coupling between load impedance and large-signal transistor behavior. Load identification is cast as an inverse electromagnetic problem, where a convolutional neural network learns the nonlinear mapping from performance features of gain, efficiency, and spectral characteristics to the reflection coefficient Γ. Validation on a 100-W Doherty PA through simulation and experimental measurements yielded a normalized mean-square error (NMSE) of -35.4 dB (mean |ΔΓ| ≈ 0.002). Behavioral modeling comparison demonstrates that Γ-aware models maintain robust accuracy under mismatch, improving NMSE by 23.8 dB over conventional 50 Ω-only approaches. This work demonstrates how deep learning techniques can solve complex electromagnetic inverse problems for adaptive RF transmitter architectures, enabling hardware-efficient implementations with compact form factor. A trained inference model and representative test-data examples will be made available at https://github.com/lab-emi/OpenDPD upon publication.

This article introduces a $4 \times 2$ -way Doherty power amplifier (PA) tailored for millimeter-wave (mm-wave) 5G applications. It incorporates an advanced output combiner that consists of four differential 2-way Doherty networks, two quadrature hybrid couplers (QHCs), and a balun to enhance the output power $P_{\text {out}}$ and improves power back-off (PBO) efficiency. Realized in 40 nm CMOS bulk technology with a core area of 1.54 $~\text {mm}^{{2}}$ , the prototype delivers a saturated power/peak gain surpassing 25.2 dBm/25.5 dB, and it demonstrates a drain efficiency (DE) exceeding 17.5%/10% at 0 dB/6 dB PBO across a 26–32 GHz band. The proposed mm-wave PA achieves error vector magnitude (EVM)/adjacent channel leakage ratio (ACLR) values of −25 dB/−33 dBc for a 2 GHz 64-quadrature amplitude modulation (QAM) orthogonal frequency-division multiplexing (OFDM) signal with 9.6 dB PAPR, operating at an average output power ( ${P}_{\text {avg}}$ ) of 11.3 dBm with an average drain efficiency ( $\text {DE}_{\text {avg}}$ ) of 4% without using digital predistortion (DPD). For a 50 MHz 1024-QAM OFDM signal with 10 dB PAPR, it achieves a ${P}_{\text {avg}}$ / $\text {DE}_{\text {avg}}$ of 7.2 dBm/2% with EVM/ACLR of −35 dB/−42 dBc without DPD.

This article presents a reconfigurable millimeter-wave (mm-wave) fully integrated transceiver (TRX) front end that comprises a power amplifier (PA) and an integrated nonreciprocal ultra-compact isolator/circulator/receiver (RX). The circulator is based on a ring quarter-wave transmission line (QTL) topology with adjusted characteristic impedances, which improves transmitter (TX)-to-antenna insertion loss and TX-to-RX isolation. The circulator’s nonreciprocal gyrator features an and-gate switching-based N-path filter while also acting as a mixer-first RX. By activating the embedded cross-coupled negative resistors, the circulator can be reconfigured as an isolator. This compact N-path filter-based circulator/isolator occupies only 0.38 mm². Over a 27.1–31.1-GHz band, the realized front end offers >20-dB TX-to-RX isolation, with a measured TX-to-antenna insertion loss of $1.7{\sim }2.2$ dB. The RX path tolerates the PA’s blocker signal, achieving 5-dBm in-band and 13-dBm out-of-band (OOB) $B_{\text {1dB}}$ . The PA delivers 15.15-dBm peak output power with 33% drain efficiency. The functionality of the proposed frequency division duplex (FDD) front end is evaluated by simultaneous TX/RX operation with a 400-MHz TX/RX modulation bandwidth and 400-MHz channel spacing. The measured AM–PM of the realized PA with the integrated isolator shows relatively high voltage standing wave ratio (VSWR) resilience at the lower power level and less robustness against VSWR around its peak output power. The front-end prototype occupies only 0.7 mm², including circulator, PA, quadrature hybrid coupler LO generators, and baseband circuits.

Digital predistortion (DPD) is a popular technique to enhance signal quality in wideband radio frequency (RF) power amplifiers (PAs). With increasing bandwidth and data rates, DPD faces significant energy consumption challenges during deployment, contrasting with its efficiency goals. State-of-the-art DPD models rely on recurrent neural networks (RNNs), whose computational complexity hinders system efficiency. This letter introduces DeltaDPD, exploring the dynamic temporal sparsity of input signals and neuronal hidden states in RNNs for energy-efficient DPD, reducing arithmetic operations and memory accesses while preserving satisfactory linearization performance. Applying a TM3.1a 200 MHz-BW 256-QAM OFDM signal to a 3.5-GHz GaN Doherty RF PA, DeltaDPD achieves −50.03 dBc in adjacent channel power ratio (ACPR), −37.22dB in normalized mean square error (NMSE) and −38.52 dB in error vector magnitude (EVM) with 52% temporal sparsity, leading to a $1.8\times $ reduction in estimated inference power. The DeltaDPD code is available at https://www.opendpd.com.

This article introduces an $N$ -way chain-weaver balanced power amplifier (PA) for millimeter-wave (mm-wave) phased-array transmitters (TXs). Taking advantage of the proposed combining network, an embedded impedance/power sensor is implemented, which can be utilized for output power regulation, built-in self-test, and load-based performance optimization. The proposed PA architecture offers linearity and gain robustness under the antenna’s frequency/time-dependent voltage standing wave ratio (VSWR). In the event of impedance mismatch, the proposed PA provides $N$ different loads equally distributed on the VSWR circle. Consequently, the performance of the PAs is the average of $N$ PAs with $N$ different loads, which makes this structure VSWR resilient. As a proof of concept, an eight-way chain-weaver balanced PA (BPA) is realized in 40-nm bulk CMOS technology, and it delivers 25.19-dBm P SAT with 16.19% PAE. The proposed PA supports a 2-GHz 64-QAM OFDM signal with 16-dBm average power, achieving $-$ 25-dB error vector magnitude (EVM). The average EVM is better than $-$ 30.3 dB without digital pre-distortion (DPD) for an “800-MHz 256-QAM OFDM” signal while generating an average output power of 12.17 dBm. The performance of the PA is also evaluated under 1.5:1–3:1 VSWR conditions. The measured small-signal gain variation under VSWR 3:1 is $\pm$ 0.7 dB. Moreover, assuming any frequency/time-dependent loading condition within the VSWR 3:1 circle, the proposed chain-weaver BPA achieves $<$ 2.8 $^{\circ}$ amplitude-to-phase (AM–PM) over 3-GHz bandwidth. Besides, the embedded impedance/power sensor accuracy outperforms the state of the art. The proposed impedance sensor can measure VSWR 3:1 by the maximum angle and magnitude errors of 12.3 $^{\circ}$ and 0.106, respectively.

Digital predistortion (DPD) enhances signal quality in wideband radio frequency (RF) power amplifiers (PAs). As signal bandwidths expand in modern radio systems, DPD’s energy consumption increasingly impacts overall system efficiency. Deep neural networks (DNNs) offer promising advancements in DPD, yet their high complexity hinders their practical deployment. This article introduces open-source mixed-precision (MP) neural networks that employ quantized low-precision fixed-point parameters for energy-efficient DPD. This approach reduces computational complexity and memory footprint, thereby lowering power consumption without compromising linearization efficacy. Applied to a 160-MHz-BW 1024-QAM OFDM signal from a digital RF PA, MP-DPD gives no performance loss against 32-bit floating-point precision DPDs, while achieving $-$ 43.75 (L)/ $-$ 45.27 (R) dBc in the adjacent channel power ratio (ACPR) and $-$ 38.72 dB in error vector magnitude (EVM). A 16-bit fixed-point-precision MP-DPD enables a 2.8 $\times$ reduction in estimated inference power. The DPD code in PyTorch is publicly available on GitHub.

This article introduces a single-supply balun-first three-way parallel Doherty power amplifier (PA) tailored for millimeter-wave (mm-wave) fifth-generation (5G) applications. It incorporates a bandwidth enhancement technique that widens the operational frequency range, enhances broadband power back-off (PBO) efficiency, and reduces impedance mismatch between differential PAs. Realized in 40-nm CMOS bulk technology with a core area of 0.77 $\text{mm}^\text{2}$ , the prototype delivers a saturated power/peak gain surpassing 20 dBm/16 dB, and it demonstrates a drain efficiency (DE) exceeding 15%/22%/33% at 9.5 dB/6 dB/0 dB PBO across a 24–30 GHz band. The proposed mm-wave PA achieves EVM/ACLR values of $-$ 24.3 dB/ $-$ 30.1 dBc for a 1-GHz 64-QAM OFDM signal, operating at an average output power (Pout) of 9.4 dBm with an average DE of 15%. For a 50-MHz 1024-QAM OFDM signal, it achieves an average Pout/DE of 8.6 dBm/12% with EVM/ACLR of $-$ 30 dB/ $-$ 36.3 dBc.

The RF performance of current-scaling digital transmitters (DTX) with polar, unsigned Cartesian, signed Cartesian, and multiphase architectures have been compared regarding power utilization of their output-stage switch banks and drain efficiency. The analysis includes various switch bank operation modes, such as switch bank sharing, segment activation interleaving, and their activation times (RF duty cycle of the segments). Current-scaling DTXs can be made compatible with high-power operations while offering high system efficiency and RF bandwidth. The average efficiency using Doherty power back-off efficiency enhancement is analyzed, and a comparison of the different proposed DTX implementations is presented.

This article presents a wideband blocker tolerant receiver (RX) for fifth-generation (5G) user equipment applications. Two programmable zeros around the channel bandwidth are introduced to sufficiently suppress the close-in blockers of 5G applications. Since the effect of zeros gradually diminishes at larger out-of-band offset frequencies, an auxiliary current-sinking path is also introduced to reduce the RX input impedance at far-out offset frequencies. Moreover, a simple second-order transimpedance amplifier (TIA) is adopted to enhance the proposed RX selectivity. The utilized TIA synthesizes two complex conjugate poles to achieve a flat gain response and $-$ 40 dB/dec roll-off. A 40-nm CMOS RX prototype occupies 1.15 $\rm{\mathbf{mm^{2}}}$ and consumes 84–140 mW from a 1.3-V supply voltage over the 0.5–3-GHz operating frequency range. The RX achieves a 160-MHz RF bandwidth, 2.6–4.2-dB noise figure, a $-$ 0.3-dBm blocker 1-dB compression point (B1dB), and an out-of-band third-order intercept point (IIP3) of 22.5 dBm. As a test case, using the 3GPP standard, a $-$ 15-dBm continuous wave (CW) close-in out-of-band blocker located at 85-MHz offset from the passband edges is applied to the RX. Thanks to the receiver’s high selectivity, the RX achieves 100% throughput while detecting 100-MS/s quadrature phase shift keying (QPSK) signal with 16 dB higher power than the reference sensitivity.

A current-mode direct-digital RF modulator (DDRM)-based transmitter (TX) architecture is proposed in this article for energy-efficient wireless applications. To demonstrate its key principles, a $2 \ttimes 13$ bit demonstrator is implemented in a 40-nm CMOS technology. This DDRM can operate standalone or as a driver for a common-gate (CG)/common-base (CB) power amplifier (PA). The proposed DDRM is based on current-steering radio frequency digital-to-analog converters (RFDACs) that feature an extra current division path to allow the generation of the optimum current-mode class-B drive profile for the final CG/CB PA, facilitating energy-efficient TX operation without compromising linearity. For this purpose, the DDRM uses signed-IQ mapping combined with a class-B harmonic rejection (HR) technique. In addition, an advanced dynamic biasing technique is introduced to further enhance the TX line-up efficiency in deep power back-off (PBO) region. The DDRM driver standalone can provide 19.6-dBm RF peak output power. It supports a “160-MHz 256-QAM” signal at 2.4 GHz with an adjacent channel leakage ratio (ACLR) of $-$ 40.3 dBc and an error vector magnitude (EVM) of $-$ 33 dB, without using any digital pre-distortion (DPD). When connected to a CB SiGe PA, the overall TX line-up achieves an output power of 27 dBm and an overall TX system efficiency of 20%. This DPD-free TX line-up achieves an ACLR of $-$ 37.7 dBc and an EVM of $-$ 30 dB, respectively, when operating with an “80-MHz 64-QAM” signal at 2.2 GHz.