Hyunjoong Lee

This paper presents a one‑port capacitance‑to‑digital converter (CDC) for floating‑target displacement sensing. A charge‑amplifier front end employing consecutive double‑sided conversion is combined with a first‑order incremental ΔΣ extended‑counting analog-to-digital converter that provides uniform input sample weighting and a successive-approximation-register residue conversion stage. Together, these blocks intrinsically reject low‑frequency interference on the floating target while enabling short conversion time and high linearity. A detailed analysis of the charge-amplifier-based CDC clarifies the trade-offs between settling time and noise under large sensing capacitance. Fabricated in a 0.13‑μm CMOS, the prototype occupies 0.54 mm² and achieves 157.5 aF_rms input‑referred noise at 316-pF total input capacitance with a 1.407-ms conversion time, consuming 1.907 mW from 3.3‑V (analog) and 1.5‑V (digital) supplies. The modified Schreier figure-of-merit is 172.7 dB.

This paper presents a fully integrated temperature-to-digital converter (TDC) fabricated in a 0.18 μm CMOS process, employing a single bipolar junction transistor (BJT). The proposed front-end sequentially biases a single BJT at two current levels to generate a ΔVBE, thereby eliminating the need for matched BJT pairs and improving reproducibility with a one‑point calibration. All critical analog and digital blocks—including the sensing front-end, an incremental delta-sigma analog-to-digital converter, power management units, clock generators, e-fuse memory, digital processing logic, and an I²C interface—are fully integrated on-chip to enable compact and standalone operation. After one-point calibration at 30 °C, the TDC achieves an inaccuracy of ±0.23 °C (3σ) over a −40 °C to 125 °C temperature range. At a conversion time of 7.68 ms, it achieves a 6.71 mK rms resolution, corresponding to a system-level resolution figure of merit (FoM) of 75.3 pJ·K². For the sensing core, the resolution FoM is 11.8 pJ·K². A co-integrated dual-BJT TDC exhibits an inaccuracy of ±0.37 °C (3σ), validating the effectiveness of the single-BJT approach for comparison. The TDC operates from a 2.0–5.5 V supply with low supply sensitivity of 2.54 m°C/V and supports a low standby current of 420 nA at 2.0 V, enabling compact size, high accuracy, and energy efficiency for duty-cycled applications.

A high input impedance read-out integrated circuit (IC) for DC measurements has been implemented. The proposed read-out IC consists of a capacitively coupled instrumentation amplifier (CCIA) and an incremental delta-sigma ( $\Delta \Sigma )$ analog-to-digital converter (ADC). An impedance boosting technique, combining the conventional positive-feedback loop with a proposed fine current compensation loop (FCCL), is introduced to enhance the input impedance of the CCIA. Additionally, the proposed structure chops the entire signal chain at a global chopping frequency of 13.2 kHz, which is higher than the 1/ $f$ corner frequency of the CCIA’s main amplifier. This approach further increases the input impedance of the CCIA and eliminates the need for RRL and an analog low pass filter (LPF), thereby reducing circuit complexity and area. Local auto-zeroing and correlated double sampling techniques are also used to suppress the offset and 1/ $f$ noise of the read-out IC. The 18-bit ADC operates at a sampling clock of 4 MHz with a third-order cascade of integrators (CoI) digital filter. Implemented in a 0.13 $\mu $ m CMOS process, the prototype chip occupies an area of 3.808 mm $^{2}$ and draws 1.32 mA from a 5 V supply. The input impedance is boosted from 4.4 M $\Omega $ to 5.1 G $\Omega $ , corresponding to an impedance boosting factor of 1153. The measurement results show an input-referred noise of 2.4 $\mu $ V $_{\mathrm{RMS}}$ with a conversion time of 0.076 ms. The input range of the ROIC is 4.8 V and it achieves the Schreier figure of merit of 164.9 dB.

A high-efficiency integrated photovoltaic (PV) energy harvesting system based on direct current resistance (DCR) current sensing is proposed. The system employs an integrated microcontroller unit (MCU) to precisely control a high-voltage gate driver, which drives the power field-effect transistor based on sensed instantaneous voltage and current information. Power conversion efficiency is enhanced through DCR current sensing for instantaneous power computation and by achieving low on-resistance of external power field-effect transistors via high-voltage gate driver control. The MCU orchestrates sophisticated timing control between the high-voltage gate driver, sample and hold circuit, and a 12-bit analog-to-digital converter to sense inductor current, thereby achieving high tracking efficiency. The integrated circuit for the PV energy harvesting system is fabricated using 0.13 μm BCD process and operates over a wide power range from 5.5 W to 276 W. Thanks to the DCR current sensing network and precise power sensing, the system achieves a high tracking efficiency of over 99% across the power range of 11.7 W to 276 W, demonstrating exceptional stability. The system achieves a peak tracking efficiency of 99.95% and a peak power conversion efficiency of 98.74%, representing the highest efficiency and power density compared to state-of-the-art PV energy harvesting systems.

This paper presents a novel optical proximity sensor behind a display panel based on silicon nanowires. Since silicon nanowires have high photoresponsivity, they can sense the distance even when placed under the display, without using a large current for driver operation. In addition, the dark leakage current generated by silicon nanowires can be removed through the read-out integrated circuit (ROIC) in the proposed optical proximity sensor. The ROIC has a resistive-feedback transimpedance amplifier (TIA) to provide a constant voltage to silicon nanowires and to convert the photocurrent of the silicon nanowires. The auto-zeroing technique reduces the ROIC’s offset and 1/f noise. The bias sampling is applied to a 12-bit single-slope analog-digital converter to reduce noise generated in the bias circuit of the ramp generator. The digital back-end cancels the offset due to dark leakage current through the correlated double sampling technique. The proximity sensor is fabricated in a 0.18 μm CMOS process and the ROIC occupies an area of 0.18 mm2. It draws an average current of 139.4 μA from a 3 V supply, and 60.2 μA from a 1.8 V supply when the conversion time is set to 50 ms, and the current of the vertical cavity surface emitting laser (VCSEL) driver is set to 12 mA. The proximity sensor is tested under a display panel with a light transmission of 6 %. It has an input-referred root mean square noise of 323 pA. The VCSEL driving current can be varied to 7 mA, 10 mA, and 12 mA, and the optical proximity sensor can detect an object that is closer than 40 mm in all three cases.

This brief presents a 9Gb/s transmitter for intra-panel interfaces, with dual-loop calibration and a 2D binary-segmented driver. The dual-loop calibration during the training period compensates the transmitter output for the variations in operating conditions such as supply voltage and reference current. The 2D binary-segmented driver provides wide range and high resolution output characteristics, and independent adjustments for VOD, VCM and FFE strength while maintaining signal integrity. The transmitter reduces power consumption by optimizing the output for the channel. A prototype chip, fabricated in a 55nm CMOS process, occupies 0.057mm ² . It provides FFE strength from 0dB to 26.4dB, common-mode voltage from 260mV to 690mV, and differential output voltage from 100mVppd to 1200mVppd, which varies by less than 4% across supply voltage and reference current variations. It also consumes 36mW at a data-rate of 9Gb/s with a 1.2V supply.

This paper presents a digital capacitive MEMS microphone for speech recognition with fast wake-up feature using a sound activity detector. The proposed microphone wakes up only when an acoustic event within the voice-band occurs using the sound activity detector, which can significantly reduce the average current consumption. All wake-up processes are performed on-chip, which enables the fast wake-up feature to prevent missing keywords. In addition, the proposed deglitching technique is applied to prevent the sound activity detector from responding to non-acoustic signals such as glitch signals. An auxiliary low-dropout regulator is used to further reduce the wake-up time. Our microphone consumes only 16 μA in deep-sleep mode. In active mode, a high-performance readout circuit converts the voice signal into a digital signal. The proposed microphone achieves an A-weighted signal-to-noise ratio (SNR) of 62.8 dBA and an acoustic overload point of 119.4 dB sound pressure level. The readout circuit itself of our microphone, fabricated in a 0.18 μm CMOS process, has an A-weighted SNR of 65.8 dBA.

Along with the trend to reduce the power consumption of mobile devices, interface circuits such as ADCs should also be designed to operate reliably at low supply voltages without compromising production yield. We present a high-fidelity audio Σ ADC suitable for low-voltage mobile applications, based on a new multi-bit quantizer. Its effective resolution is increased economically by augmenting an internal low-resolution quantizer with the proposed multi-rate noise-shaping technique. Fabricated in a 0.13 μm CMOS technology, our ADC uses 3.5 mW at 1.2 V, and achieved an A-weighted DR of 108.9 dB and a peak SNDR of 101.4 dB.