Suhwan Kim

This paper presents a high-bandwidth memory (HBM) PHY interface employing a reconfigurable differentiator-based crosstalk cancellation (XTC) scheme to mitigate coupling noise arising in high-density silicon interposer channels. By introducing a novel analysis of RC-dominant channels from the perspective of group delay, the proposed XTC achieves precise delay matching by optimal differentiator parameter selection, without requiring additional hardware. Furthermore, the self-loading induced by multiple-aggressor XTC is compensated by reconfiguring the XTC scheme into a bandwidth extension scheme in which the bi-directional signaling nature of HBM interface is leveraged. Additionally, the merged adder with multiple-XTC and decision-feedback equalization (DFE) is proposed to provide improved offset and power performance. Fabricated in a 28-nm CMOS process, the prototype transceiver achieves an edge density of 15 Tb/s/mm and energy efficiency of 0.53 pJ/bit with high-density on-chip channels of 7.5-dB Nyquist loss. The proposed XTC technique reduces the crosstalk-induced jitter (CIJ) by four aggressors by 72.4% at a signal-to-crosstalk ratio of 0.45 dB, achieving an eye-opening of 0.42 UI at a $10^{-12}$ bit error rate (BER).

This paper presents an optical particulate matter (PM) sensor featuring on-chip machine learning (ML) calibration to enhance accuracy across diverse particle sizes. A programmable gain amplifier with dynamic range extension is integrated to improve the precision of low PM concentration measurements (3), fully utilizing the analog-to-digital converter’s (ADC) dynamic range. The sensor employs an ML calibration approach combining least mean square (LMS) error and singular value decomposition (SVD)-based pseudoinverse matrix to mitigate variations in modules and components, significantly enhancing system reliability. These innovations enable accurate classification of four PM categories: PM_1.0, PM_2.5, PM_4.0, and PM_10.0. For particle concentrations above 30 μg/m³, the maximum measurement error is +8.85% / -8.84%; for concentrations below 30 μg/m³, the error is within +2.9 μg/m³ / -2.6 μg/m³. Fabricated using a standard 0.13 μm CMOS process, the 5.80 mm² read-out integrated circuit compensates for module-level and component-level variations, ensuring robust and reliable performance.

This article presents a high-resolution programmable-gain incremental delta-sigma (ΔΣ) analog-to-digital converter (ADC) optimized for high-accuracy bridge transducer measurements. The proposed design incorporates a triple-sampling (TRS) technique and an auto-zeroing (AZ) integrator that are effectively combined to suppress DC offset and 1/f noise, reduce input-referred noise (IRN), and improve effective resolution (ER). Implemented using a switched-capacitor (SC) ΔΣ modulator architecture, the proposed ADC provides accurate gain control without the need for additional power-hungry amplifiers. With the AZ-TRS integrator, a low IRN of 1.03 μV_RMS is achieved. Furthermore, the ADC demonstrates an integral nonlinearity (INL) of ±4 ppm across all gain settings, with a maximum gain of 13. Additionally, it achieves power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) values of 117.1 dB and 122.0 dB, respectively. The prototype chip was fabricated using a 0.18-μm CMOS process, and the ΔΣ modulator occupies a compact area of 0.34 mm². The ADC operates with a supply voltage of 3.0 V and a current consumption of 361 μA for the analog circuitry, while the digital filter consumes 36 μA at 1.8 V.

The increasing demand for high dynamic range (HDR), power efficiency, and high resolution has driven the adoption of single-exposure dual conversion gain (DCG) techniques. This paper proposes an adaptive split current source to optimize power consumption in single-exposure DCG readouts. By splitting the comparator bias current, the power consumption of the digitizer array can be adaptively optimized based on the conversion gain (CG) of pixel in single-exposure DCG operation. Additional power-saving features including decision-feedback and auto-zeroing (AZ) power-down techniques are also implemented to further improve power efficiency. The proposed digitizer chip was fabricated in a 28 nm CMOS process, achieving a power consumption reduction of 44.5% in comparator. The integral nonlinearity (INL) was measured as +2.67/–2.34 LSB in high conversion gain (HCG) and +2.95/–1.92 LSB in low conversion gain (LCG). The input-referred random noise (RN) values of 2.17 LSB (HCG) and 2.41 LSB (LCG) were measured at an analog gain of 16, corresponding to 93 μV_rms and 103 μV_rms, respectively. The prototype chip shows a highly competitive figure of merit (FoM) of 2.41 mV∙pJ/pixel/frame.

This study analyzed the design and performance evaluation methodologies for a high-precision, low-offset, low 1/f corner, and high-linearity read-out integrated circuit (ROIC) intended for DC measurement applications. Most innovative ROICs incorporate a capacitive-coupled instrumentation amplifier (CCIA) and a switched-capacitor (SC) incremental delta-sigma (ΔΣ) ADC. This paper discusses the comprehensive design methodologies, including high-level simulations using MATLAB and Simulink, behavioral modeling, and performance evaluations of high-precision ROIC, including incremental ΔΣ ADCs. It also details the implementation of dynamic offset cancellation (DOC) techniques, such as correlated double sampling (CDS) and chopper stabilization (CHS), to achieve a low offset and a low 1/f corner frequency. Furthermore, the paper includes the measurement methodologies for verifying the critical performance metrics, such as offset, gain error, linearity, common-mode rejection ratio (CMRR), power supply rejection ratio (PSRR), and noise characteristics. The proposed design and verification methodologies aim to enhance the accuracy, stability, and energy efficiency of high-precision DC measurement systems.

A high input impedance read-out integrated circuit (IC) for DC measurements has been implemented. The proposed read-out IC consists of a capacitively coupled instrumentation amplifier (CCIA) and an incremental delta-sigma ( $\Delta \Sigma )$ analog-to-digital converter (ADC). An impedance boosting technique, combining the conventional positive-feedback loop with a proposed fine current compensation loop (FCCL), is introduced to enhance the input impedance of the CCIA. Additionally, the proposed structure chops the entire signal chain at a global chopping frequency of 13.2 kHz, which is higher than the 1/ $f$ corner frequency of the CCIA’s main amplifier. This approach further increases the input impedance of the CCIA and eliminates the need for RRL and an analog low pass filter (LPF), thereby reducing circuit complexity and area. Local auto-zeroing and correlated double sampling techniques are also used to suppress the offset and 1/ $f$ noise of the read-out IC. The 18-bit ADC operates at a sampling clock of 4 MHz with a third-order cascade of integrators (CoI) digital filter. Implemented in a 0.13 $\mu $ m CMOS process, the prototype chip occupies an area of 3.808 mm $^{2}$ and draws 1.32 mA from a 5 V supply. The input impedance is boosted from 4.4 M $\Omega $ to 5.1 G $\Omega $ , corresponding to an impedance boosting factor of 1153. The measurement results show an input-referred noise of 2.4 $\mu $ V $_{\mathrm{RMS}}$ with a conversion time of 0.076 ms. The input range of the ROIC is 4.8 V and it achieves the Schreier figure of merit of 164.9 dB.

A high-efficiency integrated photovoltaic (PV) energy harvesting system based on direct current resistance (DCR) current sensing is proposed. The system employs an integrated microcontroller unit (MCU) to precisely control a high-voltage gate driver, which drives the power field-effect transistor based on sensed instantaneous voltage and current information. Power conversion efficiency is enhanced through DCR current sensing for instantaneous power computation and by achieving low on-resistance of external power field-effect transistors via high-voltage gate driver control. The MCU orchestrates sophisticated timing control between the high-voltage gate driver, sample and hold circuit, and a 12-bit analog-to-digital converter to sense inductor current, thereby achieving high tracking efficiency. The integrated circuit for the PV energy harvesting system is fabricated using 0.13 μm BCD process and operates over a wide power range from 5.5 W to 276 W. Thanks to the DCR current sensing network and precise power sensing, the system achieves a high tracking efficiency of over 99% across the power range of 11.7 W to 276 W, demonstrating exceptional stability. The system achieves a peak tracking efficiency of 99.95% and a peak power conversion efficiency of 98.74%, representing the highest efficiency and power density compared to state-of-the-art PV energy harvesting systems.

This brief presents an on-chip bias temperature instability (BTI) monitor to accurately detect performance degradation caused by negative BTI (NBTI) and positive BTI (PBTI) in DRAM periphery. The proposed BTI monitor is capable of isolated measurement of both NBTI and PBTI using a configurable pull-up and pull-down switching network. The dual-delay line topology also ensures fast measurement to minimize unwanted BTI recovery, which reduces measurement accuracy. In addition, a calibration scheme for process variation is proposed using body biasing of devices that mimics BTI-induced stress to further enhance measurement accuracy.