Ozgur Sinanoglu
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Ozgur Sinanoglu has a total of 157 co-authors. Here are the top co-authors by number of shared publications:
- Johann Knechtel
Center for Cyber Security, New York University Abu Dhabi, Abu Dhabi, UAE
47 shared publications - Satwik Patnaik
Department of Electrical and Computer Engineering, University of Delaware, Newark, DE, USA
29 shared publications - Ramesh Karri
ECE, New York University
19 shared publications - Lilas Alrahis
Khalifa University, Abu Dhabi, Abu Dhabi, United Arab Emirates
18 shared publications - Nimisha Limaye
Department of Electrical and Computer Engineering, Tandon School of Engineering, New York University, Brooklyn, NY, USA
11 shared publications - Nikhil Rangarajan
Division of Engineering, New York University Abu Dhabi, Abu Dhabi, United Arab Emirates
10 shared publications
Latest Publications
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Nothing Left to Learn: Isomorphic Graph Transformations for Hardware IP Protection
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessNothing Left to Learn: Isomorphic Graph Transformations for Hardware IP Protection
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessNetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
- Open Access
- 22 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 630-637
Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
- 22 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 630-637
Open AccessSynthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
- Open Access
- 4 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 234-249
SCREAM: Secure Channels for Real-time Evaluation of Additive Manufacturing
- 4 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 234-249
Open AccessSCREAM: Secure Channels for Real-time Evaluation of Additive Manufacturing
- Open Access
- 4 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 1892-1894
POSTER: Hector - An Agentic LLM Framework for Logic Locking
- 4 June 2026
- Published by Association for Computing Machinery (ACM)
- p. 1892-1894
Open AccessPOSTER: Hector - An Agentic LLM Framework for Logic Locking
- Open Access
TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
Hardware Trojans (HTs) remain a critical threat because learning-based detectors often overfit to narrow trigger/payload patterns and small, stylized benchmarks. We introduce TrojanGYM, an agentic, LLM-driven framework that automatically curates HT insertions to expose detector blind spots while preserving design correctness. Given high-level HT specifications, a suite of cooperating LLM agents (instantiated with GPT-4, LLaMA-3.3-70B, and Gemini-2.5Pro) proposes and refines RTL modifications that realize diverse triggers and payloads without impacting normal functionality. TrojanGYM implements a feedback-driven benchmark generation loop co-designed with HT detectors, in which constraint-aware syntactic checking and GNN-based HT detectors provide feedback that iteratively refines HT specifications and insertion strategies to better surface detector blind spots. We further propose Robust-GNN4TJ, a new implementation of the GNN4TJ with improved graph extraction, training robustness, and prediction reliability, especially on LLM-generated HT designs. On the most challenging TrojanGYM-generated benchmarks, Robust-GNN4TJ raises HT detection rates from 0% to 60% relative to a prior GNN-based detector. We instantiate TrojanGYM on SRAM, AES-128, and UART designs at RTL level, and show that it systematically produces diverse, functionally correct HTs that reach up to 83.33% evasion rates against modern GNN-based detectors, revealing robustness gaps that are not apparent when these detectors are evaluated solely on existing TrustHub-style benchmarks. Post peer-review, we will release all codes and artifacts.
Open AccessTrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
Hardware Trojans (HTs) remain a critical threat because learning-based detectors often overfit to narrow trigger/payload patterns and small, stylized benchmarks. We introduce TrojanGYM, an agentic, LLM-driven framework that automatically curates HT insertions to expose detector blind spots while preserving design correctness. Given high-level HT specifications, a suite of cooperating LLM agents (instantiated with GPT-4, LLaMA-3.3-70B, and Gemini-2.5Pro) proposes and refines RTL modifications that realize diverse triggers and payloads without impacting normal functionality. TrojanGYM implements a feedback-driven benchmark generation loop co-designed with HT detectors, in which constraint-aware syntactic checking and GNN-based HT detectors provide feedback that iteratively refines HT specifications and insertion strategies to better surface detector blind spots. We further propose Robust-GNN4TJ, a new implementation of the GNN4TJ with improved graph extraction, training robustness, and prediction reliability, especially on LLM-generated HT designs. On the most challenging TrojanGYM-generated benchmarks, Robust-GNN4TJ raises HT detection rates from 0% to 60% relative to a prior GNN-based detector. We instantiate TrojanGYM on SRAM, AES-128, and UART designs at RTL level, and show that it systematically produces diverse, functionally correct HTs that reach up to 83.33% evasion rates against modern GNN-based detectors, revealing robustness gaps that are not apparent when these detectors are evaluated solely on existing TrustHub-style benchmarks. Post peer-review, we will release all codes and artifacts.
- Open Access
Logic Encryption: This Time for Real
Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection based on logic encryption (LE). Unlike established schemes for logic locking, our work obfuscates the circuit's structure and functionality by encoding and encrypting the logic itself. We devise an end-to-end method for practical LE implementation based on standard cryptographic algorithms, key-bit randomization, simple circuit design techniques, and system-level synthesis operations, all in a correct-by-construction manner. Our extensive analysis demonstrates the remarkable efficacy of our scheme, outperforming prior art against a range of oracle-less attacks covering crucial threat vectors, all with lower design overheads. We provide a full open-source release.
Open AccessLogic Encryption: This Time for Real
Modern circuits face various threats like reverse engineering, theft of intellectual property (IP), side-channel attacks, etc. Here, we present a novel approach for IP protection based on logic encryption (LE). Unlike established schemes for logic locking, our work obfuscates the circuit's structure and functionality by encoding and encrypting the logic itself. We devise an end-to-end method for practical LE implementation based on standard cryptographic algorithms, key-bit randomization, simple circuit design techniques, and system-level synthesis operations, all in a correct-by-construction manner. Our extensive analysis demonstrates the remarkable efficacy of our scheme, outperforming prior art against a range of oracle-less attacks covering crucial threat vectors, all with lower design overheads. We provide a full open-source release.