Amr Ahmed

This article presents an ultrawideband 131–173-GHz dual-channel receiver implemented in GlobalFoundaries 45RFSOI technology for sub-THz sixth-generation (6G) applications. This system employs two V/H channels, each consisting of three-stage LNAs, a mixer, and an IF amplifier, and with a $\times$ 6 local oscillator (LO) frequency multiplier to reduce the chip LO input frequency to 17–23 GHz. The receiver achieves a state-of-the-art minimum NF of 5.7 dB with a gain of 24.4 dB, an $\text{IP}_{1\text{dB}}$ of $-$ 32.5 to $-$ 28 dBm, and an $\text{IIP}_3$ of $-$ 21 to $-$ 20 dBm. A maximum data rate of $2{$ $\times$ $} 40$ Gb/s is achieved with 32 quadrature amplitude modulation (QAM) modulation and error vector magnitudes (EVMs) of 13.5 $\%$ , 11.3 $\%$ , 9.8 $\%$ , 10.3 $\%$ , and 10.8 $\%$ in 8-GHz frequency bands centered at 136, 144, 152, 160, and 168 GHz, respectively. The chip core area is 0.77 $\text{mm}^2$ and consumes 297, with 179 mW consumed in the LO path. To the authors’ knowledge, this work achieves the lowest NF across a wide frequency range among other $D$ -band fully integrated receive channels.

This article presents a 140-GHz 2-D scalable wafer-scale transmit-receive (TRX) phased array based on radio frequency (RF) beamforming with 4-bit for both phase and gain controls. The chip is composed of $8\times8$ RF channels each having transmit and receive circuits, in addition to a TRX single-pole double-throw (SPDT) switch. One of the elements is replaced with an up/down-converter (UDC) channel composed of mixers, a $\times$ 6 LO multiplier chain, and intermediate frequency (IF) amplifiers at 9–14 GHz. The on-chip UDC channel is the interface between the IF signals on a printed circuit board (PCB) and the TX/RX RF distribution networks (DNs) on a chip. The 140-GHz DN is composed of coplanar waveguide (CPW) lines, Wilkinson dividers/combiners, and line amplifiers (LAs) to provide signal amplification. The chip occupies an area of 9.84 $\times$ 8.27 $\text{mm}^2$ and is designed and fabricated in GlobalFoundries, Malta, NY, USA, CMOS 45RFSOI technology. The chip is flipped on a low-cost organic RF PCB containing $8\times8$ patch antenna array placed at 1. $07\times1$ .22 $\text{mm}^2$ grid (0.5 $\lambda$ $\times$ 0.57 $\lambda$ at 140 GHz). The array electronically scans up to $\pm$ 60 $^{\circ}$ in the $H$ -plane and $\pm$ 38 $^{\circ}$ in the $E$ -plane for both TX and RX operations. Over-the-air (OTA) measured performance of the array demonstrates TX peak effective isotropic radiated power (EIRP) of 34-37.5 dBm at 137.5-145 GHz and RX input 1-dB compression point (P1dB) of $-$ 12 to $-$ 9 dBm at 134–143 GHz. Communication link measured for both TX and RX operations supports modulated 16-/64-quadrature amplitude modulation (QAM) signals with up to 24 Gb/s data rates with an rms EVM less than 7%/6%. In addition, a TRX phased array wireless links at 1.45 m and 5.2 meters are demonstrated with data rates up to 20 and 16 Gb/s using 16-QAM modulated signal and an rms EVM less than 9% for the 1.45 m link. To the best of the authors’ knowledge, this article presents the highest reported EIRP of 37.5 dBm for wafer-scale arrays in silicon technologies.

This article presents a wideband mm-wave passive harmonic rejection mixer (HRM) operating at 8 to 30 GHz. Resistive scaling is used to maintain high mixer linearity while rejecting the third and fifth harmonic foldings. The clock generation circuit employs a passive two-stage polyphase filter (PPF) followed by a phase interpolator capacitor divider circuit to generate the eight-phases, which eliminates clock dividers and results in efficient operation up to 30 GHz. Furthermore, the clocks are designed with overlapping 50% duty cycle, and mixer cell-to-cell isolation is achieved using a Wilkinson network in the radio frequency (RF) path. This novel design results in mm-wave operation with wide instantaneous bandwidth and greatly reduced LO power consumption. The HRM is fabricated in Global Foundries 45RFSOI CMOS process and has a measured conversion loss of $-$ 12.5 to $-$ 15.5 dB at 8–30 GHz with an instantaneous IF bandwidth of up to 8 GHz. A harmonic rejection ratio (HRR) of 27–45 dB is measured across the entire bandwidth for the second, third and fifth harmonics. The measured input P1dB and IP3 are 4.2–7 and 14.2–16.2 dBm, respectively, at 8–30 GHz. The harmonic rejection is further seen in the mixer spur table, with measured spurs of $-$ 70, $-$ 70, $-$ 60 dBm for the (2, 2), (2, 3) and (3, 3) spur for an LO frequency of 10 GHz, IF of 0.5 GHz and input signal power of 0 dBm. The total power consumption of the mixer is 200–390 mW at 8–30 GHz. This mixer is suitable for high linearity mm-wave 5G systems and wideband receivers and can be easily scaled to 20–50 GHz with similar low power consumption.

Millimeter-wave (mm-Wave) receiver (RX) array systems are widely employed to address a plethora of applications for telecommunication, radar sensing, localization, imaging, and weather monitoring. Many future mm-Wave arrays need to operate in increasingly dynamic and mobile scenarios with complicated electromagnetic (EM) environments. With their wide deployment, they are more likely to be exposed to strong interferences with unknown angle-of-arrival (AoA), frequency, and modulation schemes. In this work, we propose and implement a 23–37-GHz autonomous 2-D multiple-input and multiple-output (MIMO) RX array system with rapid full field-of-view (FoV) spatial filtering and beamforming to manage interferences and signals from unknown direction-of-arrival (DoA). The implemented RX array system architecture provides multiple deep spatial notches to relax the dynamic range requirement of downstream analog-to-digital converter (ADC) circuits and is also extendable to a larger 2-D array. The implemented RX array system includes a broadband mm-Wave frontend and two autonomous spatial filter stages (ASFs) in cascade without losing MIMO capability. A prototype is demonstrated in a 45-nm RF CMOS silicon on insulator (SOI) process. The broadband mm-Wave frontend achieves $S_{11}$ $<$ $-$ 10 dB from 26 to 36 GHz with 23–37-GHz 3-dB bandwidth and 4.9-dB minimum noise figure (NF) within the operating band. Our autonomous MIMO array demonstrates $>-$ 2.4 dB normalized array factor over full FoV and spatial notch with $>$ 27.1 dB cancellation. With two ASFs stages in cascade, we demonstrate two individual spatial notches, each with $>$ 28.3 dB spatial cancellation on unknown blockers. Furthermore, co-channel wideband modulated blockers are autonomously rejected, and the desired signal is successfully demodulated for 2.4-Gb/s 64 QAM (highest speed) with $-$ 22.02-dB error vector magnitude (EVM) rms (25% interference/signal co-channel overlap), for 0.6-Gb/s 64 QAM with $-$ 26.32-dB EVMrms (50% co-channel overlap) and for 1.2-Gb/s 64 QAM with $-$ 26.16-dB EVMrms (25% co-channel overlap).

This work presents A 26-32 GHz dual-polarization receiver (RX) with a novel autonomous polarization alignment technique in the frontend. The system employs a mm-Wave dualpolarization RX front-end with an IF analog/mixed-signal computation unit to achieve fast dual-polarization misalignment correction with no digital backend computation for mobile, dynamic, and ultra-reliable low latency communications (URLLC). It is implemented in GlobalFoundries 45RFSOI CMOS process occupying 5.67mm2 total area. It has a wideband S11 response from 25.5 GHz to 34.5 GHz and achieves an ultra-rapid μ-second polarization mismatch correction time. Polarization leakage suppression of up to 35dB is measured with the receiver gain of 28 dB and NF of 5.8 dB.

This article presents a wideband millimeter-wave (mmWave) receiver front-end that covers the frequency range from 43 to 97 GHz, supporting the operation in the major parts of the V-, E-, and W-bands. The front-end incorporates a passive mixer-first topology to achieve high linearity and wideband performance. The front-end adopts I/Q generation at the RF port, using a coupled-line coupler (CLC), rather than at the local oscillator (LO) port to mitigate the crosstalk of the overlapping I/Q LO signals especially present at high frequencies. The CLC at the RF input facilitates ultrawide band input matching. The front-end implements the multi-gate gm3 cancellation technique at the IF amplifiers to preserve the linearity and provide gain at the IF section. Image rejection capabilities using a current mode transformer-based IF 90° coupler are implemented on chip and demonstrated with measurements. The front-end prototype is fabricated on the GlobalFoundries 22-nm FD-SOI CMOS process and it demonstrates an ultra-wideband performance across the frequency range 43-97 GHz (2.25:1 bandwidth) with image rejection of up to 32 dB, IIP3 of 1.6-5.2 dBm, and gain of 15 dB. The implementation used is low-IF topology with 3.8-GHz IF frequency and 1-GHz bandwidth. Furthermore, the measurement results show that the front-end supports high-speed modulated signals of up to 6-Gbps 64QAM modulation data.