WZWei Zhu

Wei Zhu

*This is an algorithmically generated author record based on publicly available information.

Current Organizations / Institutes

The organizations/institutes from the scholar's latest article


Wei Zhu has a total of 15 co-authors. Here are the top co-authors by number of shared publications:


Latest Publications

  • Design of Compact Bidirectional Amplifier Utilizing Transformers-Stacking Technique

    by Jian Zhang, Ming Zhai, Dawei Wang, Yichen Liu, Xiangjie Yi, Ruitao Wang, Wei Zhu, Yan Wang

    Extremely high cost and form factors have become the most important reason limiting the promotion of large-scale phased-array systems for fifth-generation communication and K-/Ka-band satellite communication (SATCOM). This article presents a novel topology of ultracompact bidirectional amplifiers utilizing transformers-stacking techniques for low-cost large-scale phased arrays. In contrast to conventional bidirectional amplifier structures, this article proposes a more scalable bidirectional topology, which utilizes a magnetic self-canceling technique to stack the low-noise amplifier (LNA) into the power amplifier (PA) completely, realizing the function of the bidirectional amplifier with negligible performance penalty. In order to verify the proposed technique, the first bidirectional amplifier whose LNA mode and PA mode can work in different bands is implemented in a 45-nm CMOS SOI process for the K-/Ka-band SATCOM system. This design achieves 18.3-dBm peak saturated output power ( $P_{\text{sat}}$ ) and 15.9-dBm peak 1-dB compression output power ( $\rm{OP}_{1\,\text{dB}}$ ) in the Ka-band PA mode while maintaining a minimum noise figure (NF) of 2.46 dB in the K-band LNA mode. Furthermore, a notch filter is integrated into the three-winding transformer-based transmit/receive switches (TRSWs) to suppress the sidelobe of TX and avoid performance deterioration of the RX. Benefiting from the integration of a build-in-self notch filter, the proposed design has good gain suppression ( $>$ 45 dB) to block the interferer from other TX chips in the LNA mode. The core size of this proposed design is only 0.14 mm $^2$ , which is only 20 $\%$ –50 $\%$ of the size occupied in conventional works.


  • A Broadband Bidirectional Four-Element Four-Beam Beamformer With Compact Floorplan in a 65nm CMOS Technology

    by Jian Zhang, Ming Zhai, Yichen Liu, Xiangjie Yi, Dawei Wang, Wei Zhu, Yan Wang

    This brief presents a broadband bidirectional four-element four-beam beamformer. By utilizing the bidirectional attenuator, and phase shifter, this design achieves a 15.5 dB gain range and a 360° phase-shifting range in both receiver (RX) mode and transmitter (TX) mode. A load state switch is integrated with this design to realize more than 30 dB signal bypass of a certain path while maintaining the input/output matching unchanged to make system-level calibration more convenient. An innovative crossover design with horizontal and vertical ground shielding is proposed to suppress the crosstalk caused by the capacitive couplings at the unavoidable cross intersection in the FC network. The measurement results demonstrate that the proposed beamformer achieves < 0.12/0.26 dB root-mean-square (RMS) amplitude error and < 4.2/3.9° RMS phase error in RX/TX mode at 4.5–7 GHz. To the best of our knowledge, this design is the first broadband multi-beam beamformer that can support both RX and TX modes.


  • An Ultra-Compact Bidirectional Ka-Band Front-End Module With 3.8-dB NF and 13.5-dBm OP1 dB

    by Jian Zhang, Wei Zhu, Ruitao Wang, Chenguang Li, Dawei Wang, Sen Yin, Yan Wang

    This letter presents an ultra-compact bi-directional $Ka$ -band front-end module (FEM) in 65-nm CMOS technology. In this design, the receiver (RX) path is stacked into the transmitter (TX) path by using a magnetic self-canceling technique, improving area efficiency greatly with negligible performance penalty. Furthermore, a three-inductor coupled resonator is elaborately designed to realize the functions of the balun and input–output matching network (MN) of the RX/TX simultaneously. The measurement results demonstrate that the proposed FEM achieves 18.2-dB peak gain with a 3.8-dB minimum noise figure (NF) in RX mode, and 26-dB peak gain with 13.5-dBm 1-dB compression output power (OP $_{1\,\text{dB}}$ ) in TX mode. The core size of this proposed design is only 0.06 mm $^2$ which is only 20 $\%$ –50 $\%$ of the size occupied in prior works.


  • A 18–44 GHz Low Noise Amplifier With Input Matching and Bandwidth Extension Techniques

    by Ruitao Wang, Chenguang Li, Jian Zhang, Sen Yin, Wei Zhu, Yan Wang

    This letter presents a low noise amplifier (LNA) with a 3-dB gain bandwidth (3-dB BW) of 18-44 GHz in 65-nm CMOS technology. By deriving an analytical equation of input impedance, a co-design methodology for the first two stages of LNA that can simultaneously achieve broadband input matching and low noise figure (NF) is implemented. Weakly coupled asymmetric transformers that introduce a section of reverse parallel winding in the primary coil are designed to realize broadband interstage matching, optimize the gain flatness and boost the transconductance. The proposed LNA achieves a measured peak gain of 19.5 dB with a fractional 3-dB gain bandwidth (FBW) of 83.8%, covering the whole K-band and Ka-band. The measured NF is 2.6-3.5 dB from 20 to 43 GHz. To the best of our knowledge, the proposed LNA achieves the highest 3-dB BW and FBW with competitive NF. The measured input 1-dB gain compression point ( $IP_{1,dB}$ ) ranges from -23 to -18.5 dBm over the entire 3-dB gain bandwidth.


  • A Dual-Mode W-Band Eight-Way Parallel–Series Power-Combining PA With +18-dBm P sat and 15.1% PAE in 65-nm CMOS Technology

    by Jiawen Wang, Wei Zhu, Ruitao Wang, Yan Wang

    This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².


  • An Ultra-Compact W-band Front-End With Coupled-Line-Based Matching Network Reused T/R Switch Achieving 13.4-dBm Psat and <2-dB Switch Loss in 65-nm CMOS Technology

    by Jiawen Wang, Wei Zhu, Ruitao Wang, Yan Wang

    This letter presents a W-band front-end (FE) with integrated coupled-line-based matching network reused transmit/receive (T/R) switch in 65-nm CMOS technology. The proposed T/R switch is mainly composed of three coupled-lines and also functions as the balun, source matching, and gm-boosting network for LNA as well as load matching network for PA simultaneously in an ultra-compact way. The coupled-line-based T/R switch eliminates the lossy transistor switch in the signal path and the additional matching networks of LNA and PA, which greatly reduces the insertion loss (IL) and chip area. The T/R switch, LNA, and PA are co-designed to achieve optimal overall FE performance. Measurement results show that the IL of the proposed T/R switch introduced in TX/RX mode is less than 1.65/2.0 dB. Benefitting from the low IL, the FE achieves a maximum gain of 27.12 dB while demonstrating an 8.7 dB minimum noise figure in the RX mode. The FE also achieves maximum $P_{\mathrm{ sat}}$ /OP 1dB of 13.43/9.8 dBm with 15.4%/7.2% PAE peak / OP1dB in the TX mode. The core area of the FE is only 0.5 mm $\times $ 0.6 mm.


  • A 24–28-GHz Four-Element Phased-Array Transceiver Front End With 21.1%/16.6% Transmitter Peak/OP1dB PAE and Subdegree Phase Resolution Supporting 2.4 Gb/s in 256-QAM for 5-G Communications

    by Wei Zhu, Jiawen Wang, Xiaohan Zhang, Wei Lv, Bingbing Liao, Yanping Zhu, Yan Wang

    This article presents a power efficient 24-28-GHz four-element phased-array transceiver (TRX) front end (FE) for 5-G base stations and user equipment communications. A power efficient hybrid quadrature vector interpolation-based phase-shifting architecture is proposed to increase the TX and RX power efficiency and phase resolution. A transformer-based embedded T/R switch is proposed which minimizes TX and RX losses to ensure high TX output power and power efficiency while maintaining a low noise figure (NF) and extremely compact chip area. The 24-28-GHz four-element TRX FE is implemented in a 65-nm CMOS process (1P9M) for large-scale phased-array applications. The TX and RX paths achieve 0.8° phase resolution with <; 0.47°/0.17-dB RMS phase/gain error as well as 24-dB gain control range with 0.75-dB gain step and <; 0.1°/0.4-dB RMS gain/phase error over 24-30 GHz. The full TX path (including splitter and T/R switch) also achieves a measured 16.6-/18.9-dBm OP1dB/ P sat with 21.1%/16.6% PAE peak /OP1dB for each FE element while maintaining a minimum 4.4-dB NF in the full RX path (including combiner, T/R switch, and OFF-mode PA) at 28 GHz. Under the 64-/256-QAM modulation measurements, the full TX path achieves a state-of-the-art average output power of 13.5-/10.2-dBm per element (8.4%/3.5% full TX path PAE) with -26.4/-30.8 dB EVM and 27.8-/30.1-dB ACLR at 28 GHz, making the proposed TRX FE can be effectively deployed in both base stations and user equipment for 5-G communications. The chip size of the four-element TRX FE excluding I/O pads is only 3.4×1.1 mm 2 .