Ruitao Wang

This letter presents a broadband in-band full-duplex (IBFD) transceiver front end (FE) in 65-nm CMOS technology, which integrates an electrical balanced duplexer (EBD), a single-ended low-noise amplifier (LNA), and a differential power amplifier (PA) for 5G communication systems. Through the theoretical derivation of insertion loss and isolation of EBD, the co-design methodology of the IBFD FE is proposed. On this basis, a compact EBD with a hybrid Transformer structure is proposed to isolate the PA and LNA while providing impedance matching, thereby achieving excellent noise figure (NF) and output power. The proposed IBFD FE achieves a measured peak gain of 15.8 dB with a minimum NF of 5.9 dB for the receive path and a measured peak gain of 21.2 dB with a saturated output power ( ${P}_{\text {sat}}$ ) of 15.7 dBm for the transmit path. The measured 3-dB gain bandwidth ranges from 24 to 32 GHz, corresponding to a fractional bandwidth (FBW) of 28.6%, while the isolation of the EBD is greater than 41.5 dB in the operating frequency band.

Extremely high cost and form factors have become the most important reason limiting the promotion of large-scale phased-array systems for fifth-generation communication and K-/Ka-band satellite communication (SATCOM). This article presents a novel topology of ultracompact bidirectional amplifiers utilizing transformers-stacking techniques for low-cost large-scale phased arrays. In contrast to conventional bidirectional amplifier structures, this article proposes a more scalable bidirectional topology, which utilizes a magnetic self-canceling technique to stack the low-noise amplifier (LNA) into the power amplifier (PA) completely, realizing the function of the bidirectional amplifier with negligible performance penalty. In order to verify the proposed technique, the first bidirectional amplifier whose LNA mode and PA mode can work in different bands is implemented in a 45-nm CMOS SOI process for the K-/Ka-band SATCOM system. This design achieves 18.3-dBm peak saturated output power ( $P_{\text{sat}}$ ) and 15.9-dBm peak 1-dB compression output power ( $\rm{OP}_{1\,\text{dB}}$ ) in the Ka-band PA mode while maintaining a minimum noise figure (NF) of 2.46 dB in the K-band LNA mode. Furthermore, a notch filter is integrated into the three-winding transformer-based transmit/receive switches (TRSWs) to suppress the sidelobe of TX and avoid performance deterioration of the RX. Benefiting from the integration of a build-in-self notch filter, the proposed design has good gain suppression ( $>$ 45 dB) to block the interferer from other TX chips in the LNA mode. The core size of this proposed design is only 0.14 mm $^2$ , which is only 20 $\%$ –50 $\%$ of the size occupied in conventional works.

This paper proposes a broadband variable gain lownoise amplifier (VG-LNA) for multi-band 5G communications using 65-nm CMOS technology. Through theoretical derivation of input impedance and noise matching, a high-order matching network based on a weakly coupled asymmetrical transformer is introduced. The introduced transformer provides magnetic negative feedback, which further reduces the noise figure (NF) and achieves broadband input matching. Precise gain control of the VG-LNA is provided by five cascaded switchable attenuators in topologies of simplified T-type, T-type and π-type. To reduce the phase error between the reference state and the attenuation state, compensation capacitors and transistors are added in the parallel and series branches of the attenuator, respectively, to realize dual phase compensation. The proposed VG-LNA achieves a measured linear gain tuning range of 15.5 dB with a 0.5-dB fine tuning step. At the maximum gain state, the presented VGLNA exhibits a peak gain of 15.8 dB with a 3-dB bandwidth of 19–45 GHz, and the NF is 3.0-5.0 dB. The measured root mean square (RMS) phase error is less than 2.9over the entire 3-dB bandwidth with a minimum value of 1.4at 34 GHz. The measured RMS gain error is less than 0.27 dB, with a minimum value of 0.05 dB at 39 GHz. To the best of our knowledge, the proposed VG-LNA achieves the highest 3-dB bandwidth with low phase variation and low NF.

This article presents the design and theoretical analysis of a broadband power amplifier (PA) using the transformer-based lossy magnetically coupled resonator (MCR) network. The frequency-independent transformer loss coefficient ${\alpha}$ and its detailed extraction procedure are obtained by analyzing the double- ${\pi}$ model of the inductor. Theoretical derivation shows that for lossy transformers, broadband matching without gain ripple can only be achieved by using asymmetrical MCRs. Based on this, four new mismatch parameters ${m}$ , ${n}$ , ${\omega_0}$ , and ${Q_0}$ of asymmetrical MCRs are introduced to facilitate the analysis. A straightforward design flow based on the asymmetrical lossy MCRs to realize broadband matching including output matching and input/interstage matching is provided, which can effectively guide the implementation of broadband PAs. To demonstrate the proposed design methodology, a $Ka$ -band broadband PA is implemented in a 65-nm CMOS process. The measurement results show that the proposed PA achieves 30.9% peak power added efficiency ( $\text{PAE}_\text{max}$ ), 17.9-dBm saturated output power ( $P_\text{sat}$ ), and 16.4-dBm output 1-dB compression point ( $\text{OP}_\text{1\,dB}$ ). The measured 3-dB gain bandwidth ranges from 20 to 42 GHz, corresponding to a fractional bandwidth (FBW) of 71%, covering the entire $Ka$ -band. The PA demonstrates a flat gain with an in-band gain ripple of only 0.25 dB. To the best of the authors’ knowledge, this is the first article that thoroughly analyzes the lossy MCR matching theory.

In recent years, electronic design automation methodologies based on hierarchical multilevel bottom-up (BU) design approaches are emerging and successfully applied for RF system design. In this article, we propose a design automation methodology for the synthesis of millimeter-wave (mm-wave) systems via BU approaches, including sizing and layout generation. First, uniformly sampled passive and active component libraries with prepared layouts and S-parameter files are constructed during the offline preparation stage. Second, the BU sizing from the device level to the system level has been demonstrated via multiobjective optimization algorithms, while an improved Euclidean mapping strategy is proposed to efficiently search over circuit-level Pareto-optimal fronts (POFs) in the system-level optimization. Third, the parameterized DRC/LVS clean layout can be hierarchically generated for the system-level POFs. Compared to flat optimization at the system level, the proposed method greatly reduces the size of the search space with the highest accuracy possible and can be used for the synthesis of complex mm-wave systems. The proposed method achieves a $10\times $ runtime speedup in the system-level optimization with better optimization results.

This brief presents an adaptive analog temperature compensation (AATC) method that generates the optimal bias voltage to maintain constant gain of the millimeter-wave amplifier over an ultra-wide temperature range. The AATC method utilizes an exponential curve for high-order fitting the optimal bias voltage, which is generated by the piecewise exponential current of two differential MOS pairs operating in the subthreshold region, only requiring low power consumption and small chip area. To verify the effectiveness of the AATC method, a W-band front-end is fabricated in 65-nm CMOS technology. Benefiting from the AATC method, the measurement results show that the gain variation of the W-band front-end in both receive and transmit modes is less than ± 0.5 dB over an ultra-wide temperature range from -30 °C to 120 °C and the corresponding gain temperature coefficient is ± 0.0033 dB/°C, significantly better than the -7 dB gain variation without temperature compensation. The optimal bias voltage generation circuit based on AATC method consumes only 2 A of current under 1-V supply voltage, and occupies only 0.1 mm2.