Yan Wang

This article presents an $H$ -band CMOS receiver chipset that covers a wide frequency range of 228–324 GHz, supporting the entire band of IEEE Std. 802.15.3d. The proposed receiver employs an RF-domain quadrature mixer-first architecture to alleviate the design burden of quadrature local oscillator (LO) signal generation in $H$ -band, which is beneficial for achieving a large bandwidth. Moreover, a harmonic-enhanced $\times 12$ frequency multiplier chain (FMC) is used as an LO generator with improved bandwidth, output power ( ${P} _{\textrm {out}}$ ), and harmonic rejection ratio (HRR) to support wideband performance of the receiver. In the FMC, a double-balanced self-mixing (DBSM) tripler is proposed to achieve a superior fundamental rejection ratio, and a dual-mode harmonic-tuning doubler is proposed to enhance the output power of the FMC in $H$ -band. The receiver and the standalone FMC were fabricated in a 65-nm CMOS technology. Measurement results show that the FMC achieves a peak ${P} _{\textrm {out}}$ of 4.27 dBm and a 3-dB bandwidth of 218–292 GHz. Besides, the HRR of the FMC is better than 26 dBc from 228 to 310 GHz. Moreover, the proposed receiver demonstrates a wideband performance of 228–324 GHz with a minimum noise figure (NF) of 22.1 dB. The receiver also supports 16-QAM/64-QAM/128-QAM modulation in various channels of IEEE Std. 802.15.3d, and achieves a data rate of 40 Gb/s with 16-QAM modulation in Channel 57.

This work proposes a radio frequency (RF) large-signal model for silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) (including body-floating (BF) and body-contacting (BC) structures) that accurately captures the coupling effects of total ionizing dose (TID) and thermal stresses, based on the Penn State–Philips (PSP) model. The proposed model accurately describes the variations in gate control capability, mobility, and various leakage components under TID and thermal stresses. This model accurately predicts $I$ – $V$ characteristics as well as RF small- and large-signal characteristics across different hardened structures, including BF devices and various BC devices with different gate structures. A 10-GHz power amplifier (PA) is designed and fabricated, and its performance is also accurately predicted in a coupled thermal and radiation environment. In addition to prediction, this work can also proactively guide the design process and support radiation-hardened structure selection as well as cross-level co-optimization between RF device technology and RF circuit design. It provides insights and methodologies for device structure design, device modeling, and circuit design in spaceborne microwave systems.

This letter presents an effective capacitor-array-based phase calibration method for digital switched attenuators (DSAs) incorporating a tail capacitor, and introduces a compact 6-bit Q-/V-band bidirectional DSA prototype with the phase calibration enabled by capacitor arrays. The prototype exhibits an attenuation range of 31.5 dB with a 0.5-dB step size, where forward S₂₁ and reverse S₁₂ responses are nearly identical. Across the entire 42–52-GHz operating band, it achieves an insertion loss of 13 dB. Across the full-operating band, root-mean-square (rms) phase and amplitude errors are reduced from 5.6° to 10.03° and 0.3 to 0.46 dB (without calibration) to 2.8°–3.9° and 0.17–0.22dB (with calibration), respectively—validating the efficacy of the proposed phase-calibration capacitor array. In addition, the input return loss (S₁₁) is less than −20 dB, and the output return loss (S₂₂) is less than −12 dB, across the entire operating band. With a core area of 0.12 mm², the DSA features an exceptionally compact footprint compared with state-of-the-art designs.

This letter presents a broadband in-band full-duplex (IBFD) transceiver front end (FE) in 65-nm CMOS technology, which integrates an electrical balanced duplexer (EBD), a single-ended low-noise amplifier (LNA), and a differential power amplifier (PA) for 5G communication systems. Through the theoretical derivation of insertion loss and isolation of EBD, the co-design methodology of the IBFD FE is proposed. On this basis, a compact EBD with a hybrid Transformer structure is proposed to isolate the PA and LNA while providing impedance matching, thereby achieving excellent noise figure (NF) and output power. The proposed IBFD FE achieves a measured peak gain of 15.8 dB with a minimum NF of 5.9 dB for the receive path and a measured peak gain of 21.2 dB with a saturated output power ( ${P}_{\text {sat}}$ ) of 15.7 dBm for the transmit path. The measured 3-dB gain bandwidth ranges from 24 to 32 GHz, corresponding to a fractional bandwidth (FBW) of 28.6%, while the isolation of the EBD is greater than 41.5 dB in the operating frequency band.

With the rapid advancement of chiplet and heterogenous integration technologies, delivering power through the package, RDL, and chip layers in three-dimensional space has become a fundamental challenge for high-performance SoCs. This paper provides a comprehensive overview of power delivery solutions, including LDOs, switched capacitor converters, and Buck converters. It further details and compares advanced techniques such as novel conversion topologies, control schemes, optimization strategies, and integration strategies, offering insights into overcoming the power wall in emerging 3D-ICs.

This article presents a high-gain, high-linearity power amplifier (PA) operating in the D band, applying a novel adaptive power gain and linearity compensation structure (AGLC). The proposed structure significantly enhances linearity while concurrently providing gain improvement. On the basis, this work also employs a strongly coupled and low-insertion-loss transformer to further enhance the gain. In the measurement, the proposed PA achieves a gain of 31.6 dB with a saturation output power ( $P_{\mathrm {sat}}$ ) of 12.05 dBm and an output power at 1-dB compression point ( ${\mathrm {OP}}_{\mathrm {1~dB}}$ ) of 10.18 dBm at 123 GHz. By activating the AGLC, the small-signal gain and ${\mathrm {OP}}_{\mathrm {1~dB}}$ are improved by up to 1.33 and 2.83 dB, respectively. Meanwhile, the measurement results show that AGLC can significantly reduce the AM–AM and AM–PM distortions of PA and greatly improve the output referred third-order intermodulation intercept point (OIP3). When a 64-quadrature amplitude modulation (QAM) signal is applied, the proposed PA achieves a minimum error vector magnitude (EVM) of −24 dB under a power backoff of only 5.03 dB. To the best of the authors’ knowledge, the proposed PA achieves remarkably prominent gain and linearity performance in the D band.