Hao Lu

In this work, we propose and demonstrate a technique for optimizing linearity and off-state capacitance (Coff) in dual-mode integrated gallium nitride high-electron-mobility transistors with direct current (DC) gate bias control. In the dual-mode integrated high-electron-mobility transistor (HEMT), the large-resistance bias gate near the drain serves as a modulator for transconductance (gm) and off-state capacitance. It is shown that, in power amplifier mode, adjusting the DC gate bias redistributes the electric field, effectively reduces the peak field between the gate and drain, delays carrier velocity saturation, and mitigates self-heating effects, thereby significantly improving gm under high drain voltage. Measurements demonstrate that by optimizing the DC gate bias, both the output third-order intercept point (OIP3) and the gain of the dual-mode integrated HEMT are markedly enhanced. At 8 GHz and Vd = 50 V, increasing the DC gate bias from −2 to 28 V yields a tunable range of 12.1 dB and an OIP3 of 38.6 dBm. In switching mode, applying a negative DC gate bias introduces a series capacitance and reduces the radio frequency gate capacitance formed by the two-dimensional electron gas, resulting in an ultralow Coff of approximately 5 fF/mm. More importantly, this approach provides a new design degree of freedom: simply varying the DC level of the gate bias enables continuous tuning of the device's linearity, gain, and isolation.

The development of gallium nitride (GaN) devices toward higher power density and frequency has been seriously limited by self-heating effects, which significantly impact device performance. Although the integration with diamond provides a promising solution for GaN thermal management, the thermal boundary resistance (TBR) at the diamond/GaN interface remains the main factor limiting high-power-density operation. In this work, a molecular dynamics-modified diffuse mismatch model is established to analyze the thermal transport across the diamond/GaN interfaces with the impact of inner carbon diffusion. The deviation between the simulation results and the experiments is within 10%. This model effectively overcomes the challenges associated with mismatched mixed interatomic potentials in multi-material heterostructures. It enables the quantitative decomposition of complex interlayer structures to isolate specific thermal contributions. Crucially, the study reveals a compensation mechanism of TBR, where diffusion-enhanced transport mitigates thickness-induced penalties. This finding defines a high-stability process window, providing vital guidance for optimizing heat dissipation in diamond/GaN hetero-integration.

Gallium nitride (GaN)-on-GaN high-electron-mobility transistors (HEMTs) are acting as candidates with potential for high-frequency and high-power RF electronics in future due to their superior material quality and extremely low dislocation density. Despite these advantages, their application is limited by several challenges, including leakage current at the epilayer/substrate interface, difficulties in achieving low ohmic contact resistance, and thermal degradation arising from high power density operation. This review summarizes recent progress in understanding and mitigating these issues through interface engineering, optimized buffer and substrate doping, advanced ohmic contact techniques, and improved thermal management strategies. Developments in radiation hardness design and innovative device structures such as MIS-HEMTs and Fin-HEMTs structures further highlight the technological potential of the GaN-on-GaN platform. In the future, continued advances in epitaxy, high-field reliability, thermal engineering and packaging will be critical to fully release capabilities of GaN-on-GaN devices in the high-frequency and high-power application environment. It also outlines key research directions, including the need for integrated electrothermal co-design and mature packaging solutions tailored to the complex operating conditions that are possible in future GaN-on-GaN RF systems.

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This letter presents high-performance millimeter-wave InGaN channel double-heterostructure high-electron-mobility transistors (DH-HEMTs) fabricated using a recess gate oxidation process. The device with a 2 μm source-drain distance achieves a remarkable breakdown voltage of 76 V. When subjected to off-state high field bias conditions (-8 V, 30 V), the device exhibits a low saturation current collapse ratio of 8.1%. In 30 GHz large-signal power measurements, the device achieves a high saturation power density of 9.6 W/mm at V_DS=28 V and a high power-added efficiency (PAE) of 48.54% at V_DS=14 V. High-temperature stability test of the InGaN channel DH-HEMTs was also evaluated. These results substantiate the significant potential of InGaN channel DH-HEMTs for millimeter-wave applications.

In this article, we present gold-free AlGaN/GaN high electron mobility transistors (HEMTs) fabricated on SiC substrates using an Al–Si alloy gate fabrication process. The proposed devices incorporate a two-step deposited (TSD) Ti/Al/Ti/TiN metal stack with high-dose ion-implanted ohmic regions and implement an ohmic trench etching technique. This design achieves an ultralow ohmic contact resistance ( ${R}_{\text {C}}\text {)}$ of $0.18~\Omega~\cdot $ mm and a highly uniform surface morphology with a root-mean-squared (rms) roughness of 2.33 nm. In addition, the gate electrode employs a Ti/AlSi metal stack that is fully compatible with Si-based CMOS technology. Owing to the superior ohmic contact properties, the fabricated HEMTs exhibit a peak transconductance ( ${g}_{\text {m}}\text {)}$ of 302.2mS/mm and a saturation drain current ( ${I}_{\text {D, {max}}}\text {)}$ of 1.26 A/mm. Small-signal radio frequency (RF) measurements yield a cutoff frequency ( ${f}_{\text {T}}\text {)}$ of 23.9 GHz and a maximum oscillation frequency ( ${f}_{\max }\text {)}$ of 38.9 GHz. Furthermore, the TSD HEMT demonstrates an output power density ( ${P}_{\text {sat}}\text {)}$ of 3.9 W/mm and a peak power-added efficiency (PAE) of 63.1% at 3.6GHz. These findings highlight the potential of this approach in advancing high-performance and low-cost Au-free GaN HEMTs for sub-6 GHz RF applications.

In this article, a fully vertical $\beta $ -Ga₂O₃ heterojunction barrier Schottky (HJBS) diode utilizing a sputtered p-gallium nitride (GaN) layer is reported. The device exhibits a high destructive breakdown voltage (BV) of 4335V, a turn-on voltage ( ${V}_{\textit {on}}\text {)}$ of 0.8V, and a specific on-resistance ( ${R}_{\textit {on},\textit {sp}}\text {)}$ of 6.79m $\Omega \cdot $ cm², resulting in an outstanding Baliga’s figure of merit (BFOM) of 2.77GW/cm². This high performance is primarily attributed to the effective electric-field modulation introduced by the p-GaN layer beneath the anode, which suppresses peak electric-field crowding and significantly delays the onset of breakdown. To further validate the material quality and structural integrity of the sputtered p-GaN layer, comprehensive characterization using scanning transmission electron microscopy (STEM), X-ray diffraction (XRD), and transmission electron microscopy (TEM) was conducted, demonstrating a dense morphology and well-oriented crystalline structure. These results confirm that sputtering is a viable and promising approach for integrating p-GaN, which is particularly important in the absence of effective p-type doping technology in $\beta $ -Ga₂O₃. Furthermore, temperature-dependent–current–voltage ( $I$ – $V$ – ${T}\text {)}$ measurements were carried out to investigate the reverse leakage transport mechanisms. It was found that in the low reverse voltage range (−1to −20V), the Poole–Frenkel (PF) emission dominates, with a trap barrier height ( ${q}\phi _{t}\text {)}$ of 0.74eV. With increasing reverse bias (−20to −200V), the dominant transport mechanism transitions to 3-D Mott variable-range hopping (3-D Mott–VRH).

In this article, we introduce a new analytical model for determining the threshold voltage ( ${V} {_{\text {TH}}}$ ) in charge-trap-based hybrid gate-stack enhancement-mode (E-mode) AlGaN/GaN MIS-high electron mobility transistors (HEMTs). The ${V} {_{\text {TH}}}$ expression is derived by simultaneously solving the potential balance and interfacial Gauss equations based on band and charge distribution analyses, with the stored charge in the charge-trapping layer (CTL) evaluated considering both Wentzel–Kramers–Brillouin (WKB)-based tunneling and thermally activated emission probabilities. The model examines how ${V} {_{\text {TH}}}$ depends on structural parameters across three CTL thickness regimes: thin, where CTL thickness has minimal effect, but the blocking layer thickness dominates; intermediate, where both CTL thickness and trapped charge influence ${V} {_{\text {TH}}}$ ; and thick, where trapped charge is negligible and ${V} {_{\text {TH}}}$ decreases linearly with increasing CTL thickness. The model’s accuracy was validated by TCAD simulation, and the dependence of ${V} {_{\text {TH}}}$ on various initialization voltages and temperature was analyzed. The results offer valuable guidance for optimizing the structure and designing charge-trap-based hybrid gate-stack E-mode GaN MIS-HEMTs.

This study investigates the thermal dissipation capability and electrical performance of GaN-on-SiC high electron mobility transistors (HEMTs) through the thermal design of the GaN epilayer. The Debye–Callaway model was employed to analyze the relationship between impurity concentrations, GaN thickness, and GaN thermal conductivity. An optimized Fe/C co-doped buffer design was proposed to mitigate the effect of Fe impurities on thermal conduction within GaN epilayers. The thermal conductivity of the GaN epilayer was extracted through transducer-less transient thermoreflectance, which was improved by 40 W/m K compared to the reference structure, resulting in a 25 °C reduction in device peak temperature at a dissipated power density of 10 W/mm. Consequently, the output power density of the GaN HEMTs with the designed Fe/C co-doped buffer was improved from 16.4 to 19.1 W/mm, and the power added efficiency increased from 48.0% to 52.3% at 3.6 GHz under Vd = 70 V, illustrating the critical role of the thermal design for the GaN epilayer in advancing the RF power performance of GaN-based HEMTs.