Meng Zhang

In this Letter, the gate transport mechanism and the positive bias temperature instability in an E-mode GaN high electron mobility transistor (HEMT) with a p-i-n junction gate are investigated. The fabricated device demonstrates remarkable normally off characteristics with a high threshold voltage of 2.8 V at room temperature. Comprehensive electrical characterization identifies Poole–Frenkel emission as the dominant gate conduction mechanism, with potential barrier heights of 0.45 and 0.47 eV extracted from temperature-dependent gate leakage. Capacitance-based deep-level transient spectroscopy reveals two distinct trap states in the p-GaN layer located at 0.54 and 0.88 eV above the valence band, respectively. The positive bias temperature instability characteristics and their underlying mechanisms are also analyzed. This study reveals the material–electrical correlation mechanism in p-i-n junction gate HEMTs, providing a theoretical foundation for the further design of highly reliable p-GaN HEMTs.

In this work, we propose and demonstrate a technique for optimizing linearity and off-state capacitance (Coff) in dual-mode integrated gallium nitride high-electron-mobility transistors with direct current (DC) gate bias control. In the dual-mode integrated high-electron-mobility transistor (HEMT), the large-resistance bias gate near the drain serves as a modulator for transconductance (gm) and off-state capacitance. It is shown that, in power amplifier mode, adjusting the DC gate bias redistributes the electric field, effectively reduces the peak field between the gate and drain, delays carrier velocity saturation, and mitigates self-heating effects, thereby significantly improving gm under high drain voltage. Measurements demonstrate that by optimizing the DC gate bias, both the output third-order intercept point (OIP3) and the gain of the dual-mode integrated HEMT are markedly enhanced. At 8 GHz and Vd = 50 V, increasing the DC gate bias from −2 to 28 V yields a tunable range of 12.1 dB and an OIP3 of 38.6 dBm. In switching mode, applying a negative DC gate bias introduces a series capacitance and reduces the radio frequency gate capacitance formed by the two-dimensional electron gas, resulting in an ultralow Coff of approximately 5 fF/mm. More importantly, this approach provides a new design degree of freedom: simply varying the DC level of the gate bias enables continuous tuning of the device's linearity, gain, and isolation.

The development of gallium nitride (GaN) devices toward higher power density and frequency has been seriously limited by self-heating effects, which significantly impact device performance. Although the integration with diamond provides a promising solution for GaN thermal management, the thermal boundary resistance (TBR) at the diamond/GaN interface remains the main factor limiting high-power-density operation. In this work, a molecular dynamics-modified diffuse mismatch model is established to analyze the thermal transport across the diamond/GaN interfaces with the impact of inner carbon diffusion. The deviation between the simulation results and the experiments is within 10%. This model effectively overcomes the challenges associated with mismatched mixed interatomic potentials in multi-material heterostructures. It enables the quantitative decomposition of complex interlayer structures to isolate specific thermal contributions. Crucially, the study reveals a compensation mechanism of TBR, where diffusion-enhanced transport mitigates thickness-induced penalties. This finding defines a high-stability process window, providing vital guidance for optimizing heat dissipation in diamond/GaN hetero-integration.

Gallium nitride (GaN)-on-GaN high-electron-mobility transistors (HEMTs) are acting as candidates with potential for high-frequency and high-power RF electronics in future due to their superior material quality and extremely low dislocation density. Despite these advantages, their application is limited by several challenges, including leakage current at the epilayer/substrate interface, difficulties in achieving low ohmic contact resistance, and thermal degradation arising from high power density operation. This review summarizes recent progress in understanding and mitigating these issues through interface engineering, optimized buffer and substrate doping, advanced ohmic contact techniques, and improved thermal management strategies. Developments in radiation hardness design and innovative device structures such as MIS-HEMTs and Fin-HEMTs structures further highlight the technological potential of the GaN-on-GaN platform. In the future, continued advances in epitaxy, high-field reliability, thermal engineering and packaging will be critical to fully release capabilities of GaN-on-GaN devices in the high-frequency and high-power application environment. It also outlines key research directions, including the need for integrated electrothermal co-design and mature packaging solutions tailored to the complex operating conditions that are possible in future GaN-on-GaN RF systems.

In this article, a fully vertical $\beta $ -Ga₂O₃ heterojunction barrier Schottky (HJBS) diode utilizing a sputtered p-gallium nitride (GaN) layer is reported. The device exhibits a high destructive breakdown voltage (BV) of 4335V, a turn-on voltage ( ${V}_{\textit {on}}\text {)}$ of 0.8V, and a specific on-resistance ( ${R}_{\textit {on},\textit {sp}}\text {)}$ of 6.79m $\Omega \cdot $ cm², resulting in an outstanding Baliga’s figure of merit (BFOM) of 2.77GW/cm². This high performance is primarily attributed to the effective electric-field modulation introduced by the p-GaN layer beneath the anode, which suppresses peak electric-field crowding and significantly delays the onset of breakdown. To further validate the material quality and structural integrity of the sputtered p-GaN layer, comprehensive characterization using scanning transmission electron microscopy (STEM), X-ray diffraction (XRD), and transmission electron microscopy (TEM) was conducted, demonstrating a dense morphology and well-oriented crystalline structure. These results confirm that sputtering is a viable and promising approach for integrating p-GaN, which is particularly important in the absence of effective p-type doping technology in $\beta $ -Ga₂O₃. Furthermore, temperature-dependent–current–voltage ( $I$ – $V$ – ${T}\text {)}$ measurements were carried out to investigate the reverse leakage transport mechanisms. It was found that in the low reverse voltage range (−1to −20V), the Poole–Frenkel (PF) emission dominates, with a trap barrier height ( ${q}\phi _{t}\text {)}$ of 0.74eV. With increasing reverse bias (−20to −200V), the dominant transport mechanism transitions to 3-D Mott variable-range hopping (3-D Mott–VRH).

In this article, we introduce a new analytical model for determining the threshold voltage ( ${V} {_{\text {TH}}}$ ) in charge-trap-based hybrid gate-stack enhancement-mode (E-mode) AlGaN/GaN MIS-high electron mobility transistors (HEMTs). The ${V} {_{\text {TH}}}$ expression is derived by simultaneously solving the potential balance and interfacial Gauss equations based on band and charge distribution analyses, with the stored charge in the charge-trapping layer (CTL) evaluated considering both Wentzel–Kramers–Brillouin (WKB)-based tunneling and thermally activated emission probabilities. The model examines how ${V} {_{\text {TH}}}$ depends on structural parameters across three CTL thickness regimes: thin, where CTL thickness has minimal effect, but the blocking layer thickness dominates; intermediate, where both CTL thickness and trapped charge influence ${V} {_{\text {TH}}}$ ; and thick, where trapped charge is negligible and ${V} {_{\text {TH}}}$ decreases linearly with increasing CTL thickness. The model’s accuracy was validated by TCAD simulation, and the dependence of ${V} {_{\text {TH}}}$ on various initialization voltages and temperature was analyzed. The results offer valuable guidance for optimizing the structure and designing charge-trap-based hybrid gate-stack E-mode GaN MIS-HEMTs.

This study investigates the thermal dissipation capability and electrical performance of GaN-on-SiC high electron mobility transistors (HEMTs) through the thermal design of the GaN epilayer. The Debye–Callaway model was employed to analyze the relationship between impurity concentrations, GaN thickness, and GaN thermal conductivity. An optimized Fe/C co-doped buffer design was proposed to mitigate the effect of Fe impurities on thermal conduction within GaN epilayers. The thermal conductivity of the GaN epilayer was extracted through transducer-less transient thermoreflectance, which was improved by 40 W/m K compared to the reference structure, resulting in a 25 °C reduction in device peak temperature at a dissipated power density of 10 W/mm. Consequently, the output power density of the GaN HEMTs with the designed Fe/C co-doped buffer was improved from 16.4 to 19.1 W/mm, and the power added efficiency increased from 48.0% to 52.3% at 3.6 GHz under Vd = 70 V, illustrating the critical role of the thermal design for the GaN epilayer in advancing the RF power performance of GaN-based HEMTs.

Integrating diamond with GaN provides an effective pathway to mitigate self-heating. However, the thermal boundary resistance (TBR) remains a persistent bottleneck for further heat dissipation. While carbon (C) diffusion into the SiNx interlayer is known to reduce TBR, the associated stress evolution and its impact on device performance remain underexplored. In this work, the synergistic regulation of heat transport and electrical performance induced by C diffusion was systematically investigated. Transmission electron microscopy (TEM) was employed to characterize the interfacial microstructure and the influence of C diffusion on the interface. To further assess the resulting impact on heat dissipation, transient thermoreflectance was utilized to precisely quantify the thermal transport within the heterostructures. Classical molecular dynamics (MD) simulations were then performed to analyze the underlying physical mechanisms, revealing that intensifying C diffusion increases the phonon density of states overlap and effectively reduces the TBR. Furthermore, the intrinsic stress was quantified through geometric phase analysis (GPA) based on TEM images, demonstrating that the stress induced during the diffusion process propagates to the AlGaN/GaN heterostructure. Crucially, this stress modulation enhances the piezoelectric polarization by approximately 32%, resulting in a 5% increase in the two-dimensional electron gas (2DEG) sheet density. These findings provide a comprehensive strategy for optimizing the thermal management and mechanical reliability of high-power GaN devices.

Self-heating effects severely limit the performance of gallium nitride high-electron-mobility transistors (GaN HEMTs) in high-power radio frequency (RF) applications. Diamond capping technology leveraging diamond’s exceptional thermal conductivity (>2000 W/m·K) has emerged as a highly promising near-junction cooling solution. However, its integration with GaN HEMTs faces challenges including lattice/thermal mismatch, high thermal boundary resistance (TBR), and process compatibility. This review summarizes recent progress in high-thermal-conductivity diamond film growth, TBR optimization, thermal simulations, and the integrated process with GaN devices. These technological breakthroughs enable diamond-capped GaN HEMTs with an excellent comprehensive performance. Continued advances in these fields will be critical for fully releasing the capabilities of diamond capping technology for GaN HEMTs in high-frequency and high-power applications.