Rakshith Saligram

Cryogenic CMOS is a promising technology for high performance computing due to its improvement in subthreshold slope, carrier mobilities and reduced wire resistance. The threshold voltage (V_th) increase at 77K can be mitigated by metal gate work function (PHIG) engineering to achieve matched off current (I_off) further enhancing the device performance allowing us to operate at very low supply voltage thereby reducing the Energy Delay Product (EDP). However, the effect of variation on noise margins of static random access memories (SRAM) deploying these matched I_off devices is very prominent especially at low supply voltages (V_dd) limiting its scaling. In this work, we propose a framework to perform V_th retargeting for cryogenic SRAM for improving noise margins in high performance cryogenic SRAM cells under variation. The proposed framework comprises of a Monte-Carlo engine which performs statistical analysis and DC characterization and a backend processing engine to analyze noise margins and tune the PHIG. To demonstrate the framework, we use calibrated 14nm FinFET models at 300K and 77K. First, we analyze the logic blocks using iso-I_off devices, which yield up to 3x improvement in delay at iso-energy and a 4.5x reduction in energy at iso-delay. Next, we study the effect of V_th variation on the device currents. Finally, the framework is deployed to tune PHIG, and results show that it can enhance the noise margins by 23%, 31% and 19% for hold, read and write operations respectively at 77K compared to iso-I_off devices. Further, a 1kb SRAM array has been simulated using iso-I_off tuned peripherals and framework tuned SRAM cells, and it shows 5.4x reduction in read/write energies along with 1.2x delay reduction and better noise margins at 77K compared to 300K.

This paper introduces a Computing-In-Memory based Spiking Neural Network (SNN) architecture for cryogenic operation of CMOS (Cryo-SNN). The paper demonstrates design strategies to improve energy efficiency of Cryo-SNN by coupling low-voltage operation at cryogenic temperature with innovative design of neuron circuits optimized for cryogenic conditions. By exploiting the enhanced device characteristics of 14 nm FinFET transistors at cryogenic temperatures, our architecture outlines critical adaptations to SNN components for optimal functionality in extreme environments. The circuit simulation using measurement calibrated 14nm FinFET models shows that a Cryo-SNN designed for MNIST classification operates with 4.54X improved energy-delay-product (EDP) over room temperature operation while maintaining similar accuracy. Further, the paper designs an optimized SNN architecture for autonomous health monitoring of miniaturized satellites at cryogenic temperature consuming less than 1mW of power.

Cryogenic operation of CMOS transistors (i.e., cryo-CMOS) effectively brings an ultra-steep sub-threshold slope and ultra-low leakage, enabling high energy efficiency with appropriate tuning of threshold voltage and supply voltage. On the other hand, cryo-CMOS suffers from elevated sensitivity to process and voltage variations. To facilitate early-stage design exploration, we develop predictive BSIM-CMG model cards, which are calibrated with 14nm TCAD simulation and our experimental FinFET data from 300K to 77K. These models are scalable with temperatures from 300K down to 77K, device engineering and variations. Based on them, we benchmark various circuit examples to illustrate the tremendous potential of cryo-CMOS for energy-efficient computing, in the presence of process variations. For logic circuits, such as a canonical critical path, more than 15× reduction in total energy consumption is demonstrated at 77K for the iso-Delay condition, compared to the operation at the room temperature (RT). The presence of variations only has a marginal impact on energy efficiency, after threshold voltage and supply voltage are adaptively increased. For static noise margin (SNM), it is consistently improved at 77K. However, the impact of variations on SNM is much more pronounced than that on logic circuits.

With Copper (Cu) Interconnects causing performance bottleneck at single nanometer nodes due to increase in resistivity size effects viz., grain boundary scattering and surface scattering, there has always been scavenging for alternate interconnect materials. Although the Cu resistivity value decreases at cryogenic temperature, the problems continue to persist. In this work, we study three alternate interconnect materials specifically for 77K High Performance Compute applications. We select the materials based on their resistivity value at 77K for 7nm node computed using Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models. We analyze the delay of the interconnects, understand repeater insertion as a function of wire length, evaluate repeater count and energy at system level and perform IR drop analysis by showing through detailed analytical models that Ru, Rh and Al can provide appreciable improvements over Cu at 77K. The delay of interconnects reduces by 1-3.75% for Ru, 1.5-7.25% for Rh and 4.4-17.8% for Al across the BEOL stack while repeater counts decrease by 10%, 15% and 37% for Ru, Rh and Al respectively at 77K. We investigate thermal and reliability aspects of interconnect design including electromigration, Joule Heating and maximum allowed current densities again proving that Ru (9%), Rh (18%) and Al (63%) outperform Cu at 77K. Finally, we study the effects of various Low-k dielectric materials on the interconnect capacitance and thermal behavior for Cu as well as three alternate materials noting that, even though thermal conductivity of dielectrics decrease at 77K, the Joule Heating will not be as worse as one might expect.

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- $k$ metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- $V_{\mathrm {DD}}$ scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

At scaled nodes, Back End of Line (BEOL) interconnect resistance increases super-linearly and creates performance and energy bottlenecks. While it is known that metal resistance deceases with temperature, understanding and quantifying the behavior of interconnects from a foundry process design kit (PDK) at low temperature is critical for designing circuits and systems operating at cryogenic temperatures including Quantum and Superconducting Computers and other High-Performance Systems. In this letter we use parametric path based ring oscillators along with reference ring oscillators and Metal-on-Metal Capacitors for 22nm Fully Depleted Silicon on Insulator to measure RC delays of BEOL elements from room temperature to 4.2K. The extracted resistance of the elements show reduction of up to 30% for M1/M2, 33% for M3-M6 and 19% for Via1. With simple assumptions for interconnect structure, we perform least-squares fit of Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models with line-Edge roughness incorporated in the model using the Namba Model. The empirically fitted parameters track well with literature. The fitted model is within 3.7% error of all experimental results.