Jill Mayeda

This work explores the use of current reuse in a heterogeneous transceiver (TRX) using a 65-nm CMOS technology and a 0.1- $\mu $ m D-mode GaAs technology to remove the need of negative biases and to exploit the benefits of current reuse, such as lower P_DC dissipation, and to possibly simplify packaging. With this configuration, this TRX achieves competitive performance against other state-of-the-art works. The TX achieves measured S ${}_{21}~25.2$ dB, max. PAE of 21.8%, and P_SAT of 15.9 dBm at 20 GHz, while the RX achieves S₂₁ of 12.5 dB and NF of 3.4 dB with P ${}_{\mathbf {DC}}$ of 30 mW at 29 GHz. Measurements with modulated signals show that the RX is able to support a 400-Mbaud 256-APSK signal at 29 GHz and the TX achieves, with the same signal at 20 GHz, an error vector magnitude (EVM) of −28.2 dB with P_OUT,AVE of 4.2 dBm. To the authors’ best knowledge, this is the first work using current reuse techniques across different technologies.

This article presents a 256-element CMOS active phased-array transmitter (TX) that works at 19 GHz for low-Earth orbit (LEO) satellite applications. This work proposes a 90° coupler-end structure for circular polarization (CP) wave generation, which features low power consumption and enables dual-CP waves emitting in two directions. In addition, this work employs two calibration techniques to improve cross-polarization discrimination (XPD) in single-CP and dual-CP modes. The power consumption of the proposed structure is 9.4 W at 56-dBm average effective isotropic radiated power (EIRP), which is 40% lower than the state-of-the-art. It consumes 17.8 W at 64.7-dBm maximum EIRP. The beam-steering ability of this work can achieve ±65° with a sidelobe level <10-dBc. For the EVM measurement result, in single-CP mode, this work can support 256 amplitude-phase shift keying (APSK) modulation with a 2-Gbaud symbol rate on a 56-dBm EIRP output. In dual-CP mode, this work can support 256 APSK modulation with a 250-MBaud symbol rate on a 56-dBm EIRP output.

This work presents three different phased arrays achieving simultaneous operation for low earth orbit (LEO) satellite communication (SATCOM). The first phased array is a CMOS only transceiver (TRX) beamforming IC (BFIC) using a 65 nm CMOS process that utilizes self-duplexing antennas, which are presented to highlight the efficacy of the antennas. Next, this phased array is extended into the second phased array which includes a one path D-mode GaAs LNA and provides the foundation for the methods of taking advantage of the simultaneous operation of SATCOM to produce a small and simple printed circuit board (PCB) design while improving noise performance in the receiver (RX). Finally, the third phased array expands upon this to include a two path GaAs TRX which can highlight the use of single versus multipath beamforming chips within heterogenous TRXs and also improves the transmitter (TX) performance. The second phased array takes advantage of the simultaneous operation of SATCOM to bias the GaAs LNA by coupling some of the TX output to a 5-stage rectifier to generate a negative voltage. The third phased array uses the same method of coupling some of the TX signal to generate a negative voltage, which is done through a three-line coupler so that the GaAs PA and LNA can be biased independently. All three designs are capable of beamsteering and can support transmitting and receiving 400 MBaud 256-APSK signals simultaneously in over-the-air (OTA) measurements.

This article presents a 256-element CMOS active phased-array transmitter (TX) that works in Ka-band downlink for low earth orbit (LEO) small satellite communication (SATCOM) applications. The phased array adapts an on-chip monitor circuit which can be used to detect the amplitude and phase for calibration. The TX chip’s output 1 dB compression point (OP1dB) is 11dBm and saturated output power (Psat) is 12dBm for every path. The phased array can support single circular polarization (CP) and dual circular polarization modes. The maximum effective isotropic radiated power (EIRP) for the single CP wave can reach 64.6 dBm under a power consumption of 37.4W. The error vector magnitude (EVM) of this work can support 256APSK modulation in both single CP mode (at 2 Gbaud symbol rate) and dual CP modes (at 250Mbaud symbol rate). As for beam steering ability, the phased array can cover a beam angle of ±66°. Compared to the conventional TX, this work has a larger beam angle and EIRP without sacrificing too much power consumption.

This article introduces a compact D-band phase shifter, which achieves high-resolution phase steps and ultra-low phase error, designed for the sixth-generation (6G) mobile network. The proposed design integrates two novel circuit architectures: a feedback fine-tuning phase shifter (FFPS) provides precise phase control with fine 0.1° steps over a 22.5° range by using a feedback transmission line (TL) to enhance gain and tuning range. The second architecture is a two-mode non-uniform propagation delay phase shifter (2-mode NU-PDPS), which enables coarse phase tuning with 22.5° steps, covering a full 360° phase range. It employs non-uniform MOSFET sizing to realize ideal TL operation. In addition, two modes are introduced in the quarter-wave TL to increase phase resolution without increasing area and thus achieves a core area of 0.06 $\text {mm}^{2}$ . The proposed phase shifter operates with 0.1° steps over a 360° fine-tuning range within the frequency range of 150–160 GHz. It achieves an rms phase error of 0.68°, the lowest among reported phase shifters in this frequency range. The total power consumption is 5mW at 1.0-V VDD, with an insertion loss of −2.5dB.

This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path.With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain this jitter enhancement over different process, voltage, and temperature (PVT) variations. A proof-of-concept chip was built in 65 nm CMOS technology with an area of 0.105 mm². At an output frequency of 1.0 GHz, the rms jitter of the DPLL was decreased from 1.0 ps to 753 fs with the cost of around 0.7 mW power consumption due to the FPNC path and the calibration circuit. This jitter reduction improves FoM from - 234.4 to -236.0 dB. To confirm the effectiveness of the FPNC path and its background calibration circuit, different measurements were performed under different output frequencies, supply voltages, bandwidths, and chips, revealing a performance enhancement under all those conditions.

A D-band wideband passive single-ended upconversion mixer with controlled LO feedthrough in 65-nm CMOS process is presented in this letter. The LO feedthrough was controlled by the varactor and the neutralizing transmission line between the LO and RF ports of the mixer. In measurement, the proposed passive single-ended mixer had a conversion gain of −13.0±1.5 dB with an ultrawide 3-dB bandwidth from 110 to 160 GHz. The LO feedthrough suppression was from −38.9 to −24.4 dB at 135 GHz by changing the varactor bias. The measured OP1dB was −12.5 dBm at center frequency. The chip occupies 0.35 mm2, including pads.

A sub-THz (88–136 GHz) full-duplex (FD) phased-array transceiver (TRX) integrating an RF self-interference (SI) canceller with differential feeding FD antennas is presented in this work. The LO phase generation chain controls differential transmitter outputs for the phased-array operation. The differential feeding FD antenna with differential pairs of chips achieves over 35-dB SI suppression. The SI suppression is improved by 20 dB when the SI canceller is turned on. Without any digital-domain SI cancellation (SIC), a total SI suppression of $>$ 60 dB is achieved over a 2-GHz bandwidth. The proposed neutralized mixer with over 20-dB LO feedthrough suppression and wideband RF amplifiers support a large data rate at sub-THz frequencies. This is the world’s first demonstrated sub-THz FD phased-array TRX. In the over-the-air (OTA) measurements for FD mode, the proposed FD TRX achieves 6 Gb/s in 8PSK and 4 Gb/s in 16QAM. It also achieves a 112-Gb/s data rate for OTA TX-to-RX.

Monolithic broadband linear and high-efficiency millimeter-wave power amplifiers (mm-Wave PAs) are critically important for realizing low-power, miniaturized wideband mm-Wave phased-array systems, since these PAs can often consume about half of the overall system power budget. This work, therefore, reports fundamental research on the design of broadband mm-Wave PAs in the 5G FR2 Band (i.e., 24-52.6 GHz) in a couple of state-of-the-art semiconductor technologies for potential applications. Specifically, this work takes advantages of a 40 nm GaN/SiC technology and a 22 nm CMOS-FD (fully-depleted) SOI (silicon-on-insulator) process, together with novel integrated circuit (IC) design techniques, to realize highly-efficient broadband mm-Wave PAs in the medium output power range of ~ < 20 dBm, with broad bandwidth (BW) of ‘ 20-30 GHz and excellent broadband peak PAE > ~ 20-40%. We then proceed to report effective and considerable linearity improvement on these PAs using Digital Pre-Distortion (DPD). The data suggests one can design very broadband and linear, highly-efficient mm-Wave PAs that operate across the key 5G FR2 Band.