A 0.8–1.4-GHz Synthesizable DPLL Using a Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation
Open Access
- 3 March 2025
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 13, 40210-40225
Abstract
This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path.With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain this jitter enhancement over different process, voltage, and temperature (PVT) variations. A proof-of-concept chip was built in 65 nm CMOS technology with an area of 0.105 mm2. At an output frequency of 1.0 GHz, the rms jitter of the DPLL was decreased from 1.0 ps to 753 fs with the cost of around 0.7 mW power consumption due to the FPNC path and the calibration circuit. This jitter reduction improves FoM from - 234.4 to -236.0 dB. To confirm the effectiveness of the FPNC path and its background calibration circuit, different measurements were performed under different output frequencies, supply voltages, bandwidths, and chips, revealing a performance enhancement under all those conditions.Keywords
Funding Information
- National Institute of Information and Communications Technology (JPJ012368C00801)
- MIC (JPJ000254)
- Society of Transnational Academic Researchers Scholars Network
- VDEC in collaboration with Cadence Design Systems Inc
- Mentor Graphics Inc
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