Dingxin Xu

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at the Nyquist rate to enable fast-stream switching for MIMO stream coexistence. The TD approach achieves full phased-array reuse and delivers high array gain and spatial selectivity for each stream at the expense of generating switching harmonics. To address this issue, a non-uniform time-hopping (TH) sequence is introduced in this article to spectrally spread the switching harmonics and mitigate the direct blocker folding. A proof-of-concept phased-array receiver is fabricated in 65-nm CMOS, integrating eight RF elements in a 7.2-mm² core area and consuming 335.2 mW. Combined with DP antennas, the phased-array receiver supports $4 \times 4$ TD-MIMO across both polarizations and achieves a maximum data rate of 38.4Gb/s using eight 800-MHz 64-QAM signals in over-the-air (OTA) measurements. Benefiting from the TD-MIMO architecture, the phased-array receiver achieves 0.078 mm² and 5.23 mW per element per stream. With the proposed non-uniform TH (NUTH) dithering, deep notches are generated at switching harmonics and 42.9-dB alias suppression is achieved. The proposed phased-array receiver also demonstrates a 34-dB improvement in blocker tolerance, maintaining –30-dB EVM_rms under a 0-dBc in-band blocker sweeping across –90° to 90° field of view (FoV) in MIMO OTA measurements.

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs into three-level signals using simple delta-sigma modulators (DSMs), followed by a nine-state lookup table (LUT) to directly generate amplitude modulation (AM) and phase modulation (PM) signals. The complex coordinate rotation digital computer (CORDIC) that is widely used in polar TXs is not required. The AM signal is truncated to two levels for on/off control of an intrinsically linear 1-bit power amplifier (PA). The PA avoids the linearity and switching loss issues of conventional switched-capacitor PAs (SCPAs). The PM signal is represented with 3 bits for eight-phase generation via edge selection from a $4\times $ carrier local oscillator (LO), which offers better linearity and power efficiency than phase modulators based on multi-bit digital-to-time converters (DTCs). Therefore, the proposed approach enables simultaneous improvements in power efficiency and linearity. Fabricated in a 65-nm CMOS process, the proposed TX achieves a 33.5% peak power-added efficiency (PAE) at 24.2-dBm output power and supports wideband 50-MSymbol/s 256-quadratic-AM (QAM) signals without digital predistortion (DPD). A maximum system efficiency (SE) of 24.5% is achieved at −25.1-dB error vector magnitude (EVM), demonstrating superior performance compared to state-of-the-art DPD-less digital polar TXs.

Synthesizable frequency synthesizers implemented with digital standard cells and automatic layout synthesis have demonstrated significant potential in recent studies. However, synthesizing analog mixed-signal circuits still involves manual pre- and post-layout simulation iterations, which consumes tens of hours and prolong the overall design cycle. To tackle this challenge, we propose the Non-Linear Jitter Model (NLJM), an extension of the Non-Linear Delay Model (NLDM), which incorporates phase noise information into digital standard cell models. This approach enables the application of digital design automation techniques to synthesizable analog mixed-signal timing circuits, facilitating faster design iterations. An experiment on single-stage logic gates shows that the phase noise prediction exhibits approximately 1.5 dB error in the phase noise floor, and another experiment on ring oscillator planning demonstrates a maximum root mean squared (RMS) error of 1.56 dB in the figure of merit (FoM). Critically, the experiments also reveal that NLJM reduces simulation time by at least 99.61% compared to the analog simulator for ring oscillator evaluations.

This work presents a D-band (110–170 GHz) CMOS transceiver (TRX) chipset that covers a 56-GHz (114–170 GHz) signal-chain bandwidth. Both the transmitter (TX) and the receiver (RX) operate as heterodyne architectures with external intermediate frequency (IF) and local oscillator (LO) signals. An eight-way low- Q power-combined power amplifier (PA), a two-way low- Q power-combined low-noise amplifier (LNA), wideband-impedance-transformation passive mixers, common-source-based cascaded distributed amplifiers (DAs), and a low-loss wideband chip-to-waveguide printed circuit board (PCB) transition are proposed with improved bandwidth and linearity to support high-order wideband quadrature amplitude modulation (QAM) signals. The TRX chipset was fabricated using a 65-nm CMOS process. The TX achieves a 13-dBm saturated output power at 130 GHz with 1150-mW dc power. The RX achieves a 12-dB noise figure (NF) with 550-mW dc power. The proposed TRX chipset achieves a data rate of 200 Gb/s by 32QAM in the single-input–single-output (SISO) over-the-air (OTA) measurement at 0.32 m. A data rate of 150 Gb/s by 16QAM is realized with 43-dBi antennas at 15 m. Additionally, a 640-Gb/s 4 $\times$ 4 OTA line-of-sight multiinput multioutput (LOS-MIMO) is demonstrated at 0.52 m.

This article presents a 7-GHz fractional- N digital phase-locked loop (DPLL) without any digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter (DTC) or dither. Utilizing a cascaded fractional divider, the fractional spur offset frequency can be shifted beyond the PLL bandwidth, resulting in less fractional spur degradation at near-integer channels. A pseudo-differential DTC (PD-DTC) technique that can cancel the even-symmetric nonlinearity components is also employed to achieve a better suppression of the fractional spur. Thanks to the aforementioned two techniques, a $-$ 62.1-dBc worst-case fractional spur can be achieved without degrading the in-band PLL phase noise (PN) or PLL locking time. Occupying 0.23-mm $^{2}$ area in a 65-nm CMOS process, this PLL can achieve a 143.7-fs integrated jitter with a 100-MHz reference frequency and 8.89-mW power consumption, which translates to a figure-of-merit (FoM) of $-$ 247.4 dB.

This paper examines the research area of Digital Phase-Locked Loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of PLL design. The paper delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using Time-to-Digital and Digital-to-Time converters, as well as Bang-Bang Phase Detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.

This work presents a 6.5-to-8-GHz cascaded dual-fractional- $N$ digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer- $N$ mode and an integrated jitter of 190.8 fs in fractional- $N$ mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of $-$ 242.9 dB. The fractional spur at near-integer channel is as low as $-$ 52.79 dBc, and the reference spur is $-$ 72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm ² core area.

This letter describes a voltage-controlled oscillator (VCO) that can achieve robust flicker noise suppression when the decoupling network is not ideal. Utilizing a multitap transformer, the implicit common-mode (CM) impedance quality factor (Q factor) degradation from the parasitic resistance of the decoupling network can be avoided. Fabricated in 65-nm CMOS, the proposed VCO realizes a flicker corner (1/f3 corner) from 70 to 230 kHz across the tuning range from 4.24 to 4.80 GHz. The proposed VCO achieves a phase noise (PN) of -127.4 dBc/Hz at 1 MHz offset frequency fofst and a Figure of Merit (FoM) of 193.1 dB. The core area of the VCO is 0.29 mm2.