Ashbir Aviat Fadila

Conventional digital polar transmitters (TXs) suffer from limited power efficiency and linearity due to the multi-bit nature of intermediate signals. This work proposes a digital polar TX architecture that avoids such drawbacks by reducing the bit count of TX signals. The proposed TX oversamples and quantizes multi-bit I/Q inputs into three-level signals using simple delta-sigma modulators (DSMs), followed by a nine-state lookup table (LUT) to directly generate amplitude modulation (AM) and phase modulation (PM) signals. The complex coordinate rotation digital computer (CORDIC) that is widely used in polar TXs is not required. The AM signal is truncated to two levels for on/off control of an intrinsically linear 1-bit power amplifier (PA). The PA avoids the linearity and switching loss issues of conventional switched-capacitor PAs (SCPAs). The PM signal is represented with 3 bits for eight-phase generation via edge selection from a $4\times $ carrier local oscillator (LO), which offers better linearity and power efficiency than phase modulators based on multi-bit digital-to-time converters (DTCs). Therefore, the proposed approach enables simultaneous improvements in power efficiency and linearity. Fabricated in a 65-nm CMOS process, the proposed TX achieves a 33.5% peak power-added efficiency (PAE) at 24.2-dBm output power and supports wideband 50-MSymbol/s 256-quadratic-AM (QAM) signals without digital predistortion (DPD). A maximum system efficiency (SE) of 24.5% is achieved at −25.1-dB error vector magnitude (EVM), demonstrating superior performance compared to state-of-the-art DPD-less digital polar TXs.

Synthesizable frequency synthesizers implemented with digital standard cells and automatic layout synthesis have demonstrated significant potential in recent studies. However, synthesizing analog mixed-signal circuits still involves manual pre- and post-layout simulation iterations, which consumes tens of hours and prolong the overall design cycle. To tackle this challenge, we propose the Non-Linear Jitter Model (NLJM), an extension of the Non-Linear Delay Model (NLDM), which incorporates phase noise information into digital standard cell models. This approach enables the application of digital design automation techniques to synthesizable analog mixed-signal timing circuits, facilitating faster design iterations. An experiment on single-stage logic gates shows that the phase noise prediction exhibits approximately 1.5 dB error in the phase noise floor, and another experiment on ring oscillator planning demonstrates a maximum root mean squared (RMS) error of 1.56 dB in the figure of merit (FoM). Critically, the experiments also reveal that NLJM reduces simulation time by at least 99.61% compared to the analog simulator for ring oscillator evaluations.

This article presents a 256-element CMOS active phased-array transmitter (TX) that works in Ka-band downlink for low earth orbit (LEO) small satellite communication (SATCOM) applications. The phased array adapts an on-chip monitor circuit which can be used to detect the amplitude and phase for calibration. The TX chip’s output 1 dB compression point (OP1dB) is 11dBm and saturated output power (Psat) is 12dBm for every path. The phased array can support single circular polarization (CP) and dual circular polarization modes. The maximum effective isotropic radiated power (EIRP) for the single CP wave can reach 64.6 dBm under a power consumption of 37.4W. The error vector magnitude (EVM) of this work can support 256APSK modulation in both single CP mode (at 2 Gbaud symbol rate) and dual CP modes (at 250Mbaud symbol rate). As for beam steering ability, the phased array can cover a beam angle of ±66°. Compared to the conventional TX, this work has a larger beam angle and EIRP without sacrificing too much power consumption.

This article presents a fully synthesizable digital PLL supported by a feedforward phase noise cancellation (FPNC) path.With the FPNC path, the rms jitter of the DPLL was enhanced (reduced) by around 25% at different output frequencies. A gain mismatch calibration circuit was proposed to maintain this jitter enhancement over different process, voltage, and temperature (PVT) variations. A proof-of-concept chip was built in 65 nm CMOS technology with an area of 0.105 mm². At an output frequency of 1.0 GHz, the rms jitter of the DPLL was decreased from 1.0 ps to 753 fs with the cost of around 0.7 mW power consumption due to the FPNC path and the calibration circuit. This jitter reduction improves FoM from - 234.4 to -236.0 dB. To confirm the effectiveness of the FPNC path and its background calibration circuit, different measurements were performed under different output frequencies, supply voltages, bandwidths, and chips, revealing a performance enhancement under all those conditions.

This article presents a 7-GHz fractional- N digital phase-locked loop (DPLL) without any digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter (DTC) or dither. Utilizing a cascaded fractional divider, the fractional spur offset frequency can be shifted beyond the PLL bandwidth, resulting in less fractional spur degradation at near-integer channels. A pseudo-differential DTC (PD-DTC) technique that can cancel the even-symmetric nonlinearity components is also employed to achieve a better suppression of the fractional spur. Thanks to the aforementioned two techniques, a $-$ 62.1-dBc worst-case fractional spur can be achieved without degrading the in-band PLL phase noise (PN) or PLL locking time. Occupying 0.23-mm $^{2}$ area in a 65-nm CMOS process, this PLL can achieve a 143.7-fs integrated jitter with a 100-MHz reference frequency and 8.89-mW power consumption, which translates to a figure-of-merit (FoM) of $-$ 247.4 dB.

This work presents a 6.5-to-8-GHz cascaded dual-fractional- $N$ digital phase-locked loop (DPLL) that avoids fractional spur degradation in near-integer channels by utilizing two PLLs with fractional frequency control words (FCWs). The FCWs of the two PLLs are carefully selected to achieve the optimal fractional spur performance at the output. A 14-bit segmented digital-to-time converter (DTC) with a background nonlinearity calibration achieving a 0.05% integral nonlinearity (INL) is proposed for further fractional spur suppression. This work achieves an integrated jitter of 154.4 fs in integer- $N$ mode and an integrated jitter of 190.8 fs in fractional- $N$ mode, respectively. It consumes 14.2 mW with a 50-MHz reference, leading to a figure of merit (FoM) of $-$ 242.9 dB. The fractional spur at near-integer channel is as low as $-$ 52.79 dBc, and the reference spur is $-$ 72.4 dBc. This PLL is implemented in a 65-nm CMOS process, occupying 0.48-mm ² core area.

The open source hardware movement has made significant progress over the past few years. Increasingly, more individuals are engaging with and participating in the open source chip design community, not only to design their chips with available open source tools but also to have their designs physically fabricated and returned to them for practical use. Companies like Google have sponsored physical chip fabrication runs over the past few years, such as OpenMPW, through semiconductor CMOS processes provided by Skywater (SKY130) and GlobalFoundries (GF180) [1] . When we consider the availability of open source chip design tools, a supportive community, reliable fabrication partners, financial sponsors, and a growing infrastructure of suppliers and educators, it becomes clear that a revolution in chip design is an inevitable outcome. By leveraging existing resources provided by the open source community, this article presents the joint development of a new laser-induced graphene (LIG)-based sensor platform. The effort includes the design, fabrication, and testing of an AFE ASIC using open tools and the design and in-house fabrication of LIG sensors. The article presents the ASIC’s design process and the fabricated chip’s testing results. It demonstrates testing a wearable strain gauge LIG sensor and a temperature-sensitive LIG sensor using our AFE chip. The demonstration serves as an example of the potential to develop the sensing system into a multimodal flexible sensing platform.

This letter describes a voltage-controlled oscillator (VCO) that can achieve robust flicker noise suppression when the decoupling network is not ideal. Utilizing a multitap transformer, the implicit common-mode (CM) impedance quality factor (Q factor) degradation from the parasitic resistance of the decoupling network can be avoided. Fabricated in 65-nm CMOS, the proposed VCO realizes a flicker corner (1/f3 corner) from 70 to 230 kHz across the tuning range from 4.24 to 4.80 GHz. The proposed VCO achieves a phase noise (PN) of -127.4 dBc/Hz at 1 MHz offset frequency fofst and a Figure of Merit (FoM) of 193.1 dB. The core area of the VCO is 0.29 mm2.

This letter describes a fully synthesizable fractional- $N$ multiplexing delay-locked loop (MDLL) with a ring-oscillator-based digital-to-time converter (RO-DTC). The proposed RO-DTC can generate a wide range of time delays with only a relatively smaller number of delay cells. Since its structure is periodical, the corresponding predistortion look-up table (LUT)’s size could also be reduced. The proposed MDLL is implemented in a 65-nm CMOS process. The measured results show that the RO-DTC’s power normalized by operating frequency and tuning range is the lowest among other state-of-the-art works. The proposed MDLL achieves FoMs of −242.3 and −218.6 dB in integer- $N$ and fractional- $N$ operation modes at RF frequencies 1.04 and 1.0465 GHz. The core area is 0.0892 mm2.