Jean-Michel Reynes
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Interests
Jean-Michel Reynes has a total of 11 co-authors. Here are the top co-authors by number of shared publications:
- Fabio Coccetti
IRT Saint Exupéry 3 rue Tarfaya 31400 Toulouse France
1 shared publication - Frédéric Richardeau
Laboratoire plasma et conversion dnergie (LAPLACE), Universit de Toulouse, CNRS, lInstitut National Polytechnique de Toulouse (INPT), lUniversit Toulouse III Paul Sabatier (UPS), Toulouse, France
1 shared publication - Hervé Morel
INSA Lyon, Ecole Centrale de Lyon, CNRS, Ampre, UMR5005, Universit Claude Bernard Lyon 1, Villeurbanne, France
1 shared publication - Joao Oliveira
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication - Laurence Allirand
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication - Michel Piton
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication
Latest Publications
- Open Access
Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs
The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan.Open AccessTest Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs
The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan. - Open Access
VDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode
This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.
Open AccessVDS and VGS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode
This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by VDS and VGS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm−2. Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on RDS-ON.