Fabio Coccetti
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Fabio Coccetti has a total of 11 co-authors. Here are the top co-authors by number of shared publications:
- Alexandre Boyer
CNRS, LAAS, Toulouse, France
1 shared publication - Hervé Morel
INSA Lyon, Ecole Centrale de Lyon, CNRS, Ampre, UMR5005, Universit Claude Bernard Lyon 1, Villeurbanne, France
1 shared publication - Jean-Michel Reynes
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication - Joao Oliveira
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication - Laurence Allirand
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication - Michel Piton
IRT Saint Exupery, CS34436, 3 Rue Tarfaya, 31400 Toulouse, France
1 shared publication
Latest Publications
- Open Access
Test Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs
The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan.Open AccessTest Methodology for Short-Circuit Assessment and Safe Operation Identification for Power SiC MOSFETs
The short-circuit (SC) immunity of power silicon carbide (SiC) MOSFETs is critical for high-reliability applications, where robust monitoring and protection strategies are essential to ensure system safety. Despite their superior voltage blocking capabilities and high energy efficiency, SiC MOSFETs exhibit greater sensitivity to SC-induced degradation compared to their silicon counterparts. This increased vulnerability necessitates the precise assessment of the key SC performance metrics, such as short-circuit withstand time (), as well as a deeper understanding of the failure mechanisms. In this study, a comprehensive experimental methodology for evaluating the SC behavior of SiC MOSFETs is presented and validated using industrial references. The investigation further explores the concept of a Safe Operating Area (SOA) under SC conditions, highlighting the significant impact of quasi-simultaneous SC events on device lifetime. Additionally, an application case study demonstrates how these events can drastically reduce the device’s lifespan. - 13 October 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electromagnetic Compatibility
- Vol. 63 (3) , 858-869
Fast and Accurate Near-Field Measurement Method Using Sequential Spatial Adaptive Sampling (SSAS) Algorithm
This article presents an optimization of the sequential spatial adaptive sampling (SSAS) algorithm to accelerate near-field scanning of printed circuit boards or integrated circuits. The first originality of this approach is to configure this algorithm from the spatial distribution characteristic of near field on a planar surface. The second originality is to propose three selection criteria to adjust the targeted accuracy with the objective to reduce the measurement time. The low time-consuming algorithm selects only measurement points, which carry the most information, in order to reduce significantly the number of captured points without increasing the measurement error. The analysis of measurement results, based on this algorithm applied on two case studies, validates its effectiveness compared to the classical full regular grid sampling.
- 13 October 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electromagnetic Compatibility
- Vol. 63 (3) , 858-869
Fast and Accurate Near-Field Measurement Method Using Sequential Spatial Adaptive Sampling (SSAS) Algorithm
This article presents an optimization of the sequential spatial adaptive sampling (SSAS) algorithm to accelerate near-field scanning of printed circuit boards or integrated circuits. The first originality of this approach is to configure this algorithm from the spatial distribution characteristic of near field on a planar surface. The second originality is to propose three selection criteria to adjust the targeted accuracy with the objective to reduce the measurement time. The low time-consuming algorithm selects only measurement points, which carry the most information, in order to reduce significantly the number of captured points without increasing the measurement error. The analysis of measurement results, based on this algorithm applied on two case studies, validates its effectiveness compared to the classical full regular grid sampling.