Abanob Shehata

This article presents a 300-GHz-band amplifier-last outphasing phased-array transmitter with path mismatch calibration in a 65-nm CMOS technology. Calibration is essential for mitigating impairments in outphasing systems used for wideband communication. The transmitter integrates two independent sub-THz LO generation chains to calibrate the phase mismatch between two paths and configure the phase delay between different phased-array elements. An integrated RF outphasing amplifier calibrates the amplitude mismatch and improves the transmitter’s effective isotropic radiated power (EIRP). After calibration, the transmitter exhibits a 3.3-dB improvement in error vector magnitude and supports 16 QAM modulation at 52 Gb/s over a distance of 9 cm. It achieves a peak EIRP of 8.9 dBm at 246 GHz, with a minimum EIRP of 5.0 dBm across the frequency range from 237 to 250 GHz. An 8×1 phased-array transmitter is implemented, demonstrating a main lobe scanning range of ±12° in the $E$ -plane.

This article introduces a compact D-band phase shifter, which achieves high-resolution phase steps and ultra-low phase error, designed for the sixth-generation (6G) mobile network. The proposed design integrates two novel circuit architectures: a feedback fine-tuning phase shifter (FFPS) provides precise phase control with fine 0.1° steps over a 22.5° range by using a feedback transmission line (TL) to enhance gain and tuning range. The second architecture is a two-mode non-uniform propagation delay phase shifter (2-mode NU-PDPS), which enables coarse phase tuning with 22.5° steps, covering a full 360° phase range. It employs non-uniform MOSFET sizing to realize ideal TL operation. In addition, two modes are introduced in the quarter-wave TL to increase phase resolution without increasing area and thus achieves a core area of 0.06 $\text {mm}^{2}$ . The proposed phase shifter operates with 0.1° steps over a 360° fine-tuning range within the frequency range of 150–160 GHz. It achieves an rms phase error of 0.68°, the lowest among reported phase shifters in this frequency range. The total power consumption is 5mW at 1.0-V VDD, with an insertion loss of −2.5dB.

A D-band wideband passive single-ended upconversion mixer with controlled LO feedthrough in 65-nm CMOS process is presented in this letter. The LO feedthrough was controlled by the varactor and the neutralizing transmission line between the LO and RF ports of the mixer. In measurement, the proposed passive single-ended mixer had a conversion gain of −13.0±1.5 dB with an ultrawide 3-dB bandwidth from 110 to 160 GHz. The LO feedthrough suppression was from −38.9 to −24.4 dB at 135 GHz by changing the varactor bias. The measured OP1dB was −12.5 dBm at center frequency. The chip occupies 0.35 mm2, including pads.

This work introduces a bang-bang fractional- $N$ phase-locked loop with quantization noise shaping that overcomes the classical noise limit of a standard bang-bang phase detector. An adaptive algorithm, working in the background of the main system, guarantees optimal noise shaping across process and environmental variations. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.21 mm ² and achieves an rms jitter (integrated from 1 kHz to 100 MHz) of 69.5 fs for integer- $N$ synthesized channels, 79.7 fs for typical fractional- $N$ channels, and 99.6 fs for near-integer fractional channels with a worst case fractional spur of −51.1 dBc. The power consumption is 10.8 mW, leading to a jitter-power figure of merit of −252.8 dB and −251.6 dB for integer- $N$ and fractional- $N$ channels, respectively.