Kriti Suneja

In this paper, a review of execution of Long Short-Term Memory Accelerator on FPGA is presented. The paper starts with a brief overview on the significance of LSTM accelerators, historical background and general structure of LSTM accelerators. Then recent works in this area are highlighted. The research in this domain is focused on modifying the architecture of LSTM to overlap the computation of different stages in the network. This yields less power and higher performance as compared to the corresponding software implementation. The implementation on FPGA provides user with the ability to tradeoff resource utilization and speed of operation by adjusting the amount of parallelization for different operation such as vector multiplication and addition. This offers flexibility to adjust the computational load for different FPGA boards.

Exact computation techniques require a high amount of resources and time. But the need of today’s Electronics world is a system that is faster and requires less area. Approximate Computing has emerged as a technique that plays with the trade-off between the requirement of exact computing to improve area requirement, speed, and power performance. In this paper, a speed-efficient model for approximate matrix multiplier is proposed with the use of the Dadda compression technique followed by the Carry-Save Ahead (CSA) adder. Hardware design is modeled in Verilog. Artix-7 xc7a100t-3csg324 is used as a target device in Xilinx ISE Design Suite 14.7. ISIM simulation results and device utilization summary have been presented. Synthesis results show that the proposed design is faster, requires less area, consumes less power than published designs.