Zhiwei Sun

This Letter presents tri-gate GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) with improved high-temperature performance for a monolithic integration platform, utilizing a low-damage digital recess technique. The fin structure followed by the multiple cycles of plasma oxidation and wet oxide removal process enables threshold voltage modulation from −9.1 V (D-mode) to +1.1 V (E-mode) in MIS-HEMTs, achieved by tuning the fin width between 800 and 56 nm on the same wafer. The E-mode device shows a low subthreshold swing of 76 mV/dec, a low on-resistance of 8.2 Ω·mm, and a low hysteresis of 26 mV. The E-mode device exhibits a small threshold voltage (Vth) shift of −0.13 V from room temperature up to 200 °C leading to logic inverters of stable characteristics with an inverter threshold voltage shift of only 0.16 V from 25 to 250 °C. These results validate the monolithic integration of tri-gate GaN to be promising for high-frequency and compact mixed-signal systems.

This article presents the enhancement-mode (E-mode) GaN p -channel heterojunction field-effect transistors ( p -FETs) with p -Al $_{\text{0.05}}$ Ga $_{\text{0.95}}$ N etching-target layer (ETL). The optimized high-selectivity etching technique achieves an etch rate of approximately 1 nm/min for p -GaN, while also generating a selectivity ratio of 4:1 between p -GaN and p -Al $_{\text{0.05}}$ Ga $_{\text{0.95}}$ N. High-yield E-mode p -FET with ETL has been obtained as the etching process window was expanded to 10 min. The devices achieved the characteristics of a threshold voltage ( $\textit{V}_{\text{th}}$ ) of $-$ 1.15 V and a maximum current density ( $\textit{I}_{\textit{D},\text{max}}$ ) of 6.16 mA/mm. Furthermore, the characteristics of multiple devices demonstrate the high consistency and reproducibility of p -FETs’ $\textit{V}_{\text{th}}$ and $\textit{I}_{\text{ON}}$ , thus providing significant opportunities for developing complementary circuit integration.

In this work, we have demonstrated the Ni/Ag contacts on p-channel heterostructure field-effect transistors (p-HFETs) based on the p-GaN/AlGaN/GaN/Si platform. Using an optimal contact condition, where Ni/Ag (1/120 nm) was deposited and annealed at 550 $^{\circ}$ C for 180 s in O $_\text{2}$ ambient, a low contact resistance (27.44 $\Omega \cdot$ mm at 50 mA/mm) and a low Schottky barrier height (SBH) (0.479 eV) have been obtained. The p-HFETs with Ni/Ag contacts exhibit a very slight Schottky character, resulting in a satisfactory ON-resistance ( R $_{\biosc{on}}$ ) of 2.1 k $\Omega\cdot$ mm. Furthermore, the p-HFETs exhibit excellent electrical properties including a threshold voltage ( V $_{{\text{th}}}$ ) of $-{\text{1.91}}$ V, an ON-state current ( I $_{\biosc{on}}$ ) of 2.46 mA/mm, and an I $_{\biosc{on}}$ / I $_{\biosc{off}}$ ratio of ${\sim}$ 10 $^{\text{6}}$ . These results present a great potential of cost-effective Ni/Ag contacts on p-HFETs.