Steven Brebels

Improving the energy efficiency of wireless communication transmitters is an increasingly important target now that millimeter-wave (mm-wave) frequencies are being used. To improve the efficiency compared with classical transmit architectures that use a class A/AB power amplifier (PA), we propose here a polar transmitter that operates around 60 GHz. This transmitter is based on a radio frequency digital-to-analog converter (RF-DAC). This RF-DAC uses a switching scheme that greatly reduces signal leakage via disabled unit cells which greatly improves the output signal quality. In this way, this polar transmitter can process higher order modulation schemes at mm-wave frequencies, such as a 64-QAM, where an excellent error vector magnitude (EVM) specification is required. This mm-wave polar transmitter, prototyped in a 28-nm CMOS technology, consists of a digital PA (DPA) using 7-bit RF-DACs for amplitude modulation (AM),and an active phase shifter (PS) using two 7-bit variable gain amplifiers (VGAs) with an in-phase quadrature (IQ)-hybrid for phase modulation (PM). All the amplitude and phase samples for the RF core are accessed from an on-chip memory. Static measurements show a power gain of 21.5 dB, a saturated output power ( $P_{\text{sat}}$ ) of 12.6 dBm, and a peak drain efficiency of 25.9 $\%$ at 64 GHz. A 10.56-Gb/s 64-QAM signal at $-$ 27.8-dB EVM is demonstrated with measured core and system efficiencies of 8.5 $\%$ and 3.9 $\%$ , respectively. The transmitter consumes 159-mA current from a 0.9-V supply.

This article proposes a cryogenic inverter-based low noise amplifier (LNA) for qubit readout. Its input impedance matching is realized by a high- $Q$ ON-chip gate inductor and capacitive load through the gate-to-drain feedback capacitance of the input transistors. Cascode transistors are used to optimize the impedance matching, which results in a larger gate inductor and smaller load capacitor and hence a higher passive and inverter gain. Owing to the high passive gain and $Q$ -factor of the gate inductor at 4 K, the noise of the active stages is substantially suppressed with a negligible noise contribution of the gate inductor. Moreover, with the current re-use in the inverter topology, less power consumption is achieved for the given transconductance of transistors. The input impedance, gain, and noise analyses of the proposed LNA are performed for room temperature (RT) operation, and its noise optimization is done by taking the cryogenic operation of the devices into account. We demonstrate with the circuit analysis and measurement results that the input impedance of the LNA has a low sensitivity to variations on device parameters at cryogenic temperatures. The LNA is implemented in a 28 nm CMOS technology. It achieves 0.4–0.7 dB noise figure (NF) with 4.2 mW power consumption at 4 K, and its operating frequency is between 6–8 GHz. The LNA consumes very low power compared to the state-of-the-art cryogenic CMOS LNAs while providing similar NF performance at 4 K, which makes it suitable for dilution refrigerators.

In this work, we report on the electrical performance of an ultra-low-power cryo-CMOS single-pole-4-throw (SP4T) RF multiplexer working at 10 mK base temperature stage of a dilution refrigerator. We use the multiplexer to benchmark a superconducting qubit for the very first time and obtain qubit coherence times of over 35 μs along with an average single-qubit gate fidelity of 99.93%, which exceeds the threshold required for quantum error-correction based on surface-code. This work demonstrates the operability of superconducting qubits with ultra-low-power cryo-CMOS devices at the base temperature, paving the way for advanced co-integration schemes.