Bogdan Govoreanu
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Bogdan Govoreanu has a total of 135 co-authors. Here are the top co-authors by number of shared publications:
- Alexander Grill
IMEC
4 shared publications - Fahd A. Mohiyaddin
Intel Corporation
4 shared publications - Kristiaan De Greve
IMEC
4 shared publications - Massimo Mongillo
IMEC, Leuven, Belgium
4 shared publications - Ruoyu Li
IMEC, Leuven, Belgium
4 shared publications - Anton Potočnik
IMEC Kapeldreef 75 B-3001 Leuven Belgium
3 shared publications
Latest Publications
- Open Access
- 7 August 2026
- Published by Springer Nature in npj 2D Materials and Applications
Advances in gate stack development for p-type 2D channel FETs through sacrificial WSe2 bilayer oxidation
- 7 August 2026
- Published by Springer Nature in npj 2D Materials and Applications
Open AccessAdvances in gate stack development for p-type 2D channel FETs through sacrificial WSe2 bilayer oxidation
- Open Access
- 30 March 2026
- Published by Springer Nature in Nature Electronics
- Vol. 9 (3) , 314-323
Radiofrequency cascade readout of coupled spin qubits
Silicon spin qubits based on metal–oxide–semiconductor (MOS) technology are compatible with semiconductor manufacturing and offer a route to scalable quantum processing. However, spin readout typically relies on proximal charge sensors, which add architectural complexity and limit qubit connectivity. In situ dispersive readout techniques are more compact, which can alleviate these constrains, but exhibit limited sensitivity. Here we report a radiofrequency electron-cascade readout method that enhances the dispersive signal through alternating-current electron co-tunnelling. With this approach, we achieve an enhancement in signal-to-noise ratio of more than 35 dB, leading to a minimum integration time of 7.6 ± 0.2 µs. We demonstrate singlet-triplet readout of two-electron spins in a natural silicon planar MOS quantum dot array, and coherent spin control using the exchange interaction, which forms the basis for entangling gates. We find dephasing times of up to 500 ns and a gate quality factor that exceeds 10.
- 30 March 2026
- Published by Springer Nature in Nature Electronics
- Vol. 9 (3) , 314-323
Open AccessRadiofrequency cascade readout of coupled spin qubits
Silicon spin qubits based on metal–oxide–semiconductor (MOS) technology are compatible with semiconductor manufacturing and offer a route to scalable quantum processing. However, spin readout typically relies on proximal charge sensors, which add architectural complexity and limit qubit connectivity. In situ dispersive readout techniques are more compact, which can alleviate these constrains, but exhibit limited sensitivity. Here we report a radiofrequency electron-cascade readout method that enhances the dispersive signal through alternating-current electron co-tunnelling. With this approach, we achieve an enhancement in signal-to-noise ratio of more than 35 dB, leading to a minimum integration time of 7.6 ± 0.2 µs. We demonstrate singlet-triplet readout of two-electron spins in a natural silicon planar MOS quantum dot array, and coherent spin control using the exchange interaction, which forms the basis for entangling gates. We find dephasing times of up to 500 ns and a gate quality factor that exceeds 10.
- 3 October 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 46 (12) , 2365-2368
Controllable p-Type Doping of 2D WSe 2 pFET by Engineered Surface Charge Transfer Doping With Metal Co-Seeding
Surface charge transfer doping (SCTD) has emerged as a promising technique for doping 2D semiconductors, although it faces challenges in doping controllability, which impacts device performance. In this study, we introduce a novel approach to precisely control the p-type doping strength in solid-state SCTD for 2D WSe₂ field-effect transistors (FET) through metal co-seeding. By sequentially depositing molybdenum (Mo) and hafnium (Hf) metal seeds followed by O₂ annealing, we achieve improved doping control, while maintaining a high on/off current ratio. High-resolution transmission electron microscopy (HRTEM) images confirm the proposed co-seeding concept. This technique addresses doping controllability limitations in SCTD, enhances gate tunability, and it is viable for very-large-scale integration (VLSI) applications.
- 3 October 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 46 (12) , 2365-2368
Controllable p-Type Doping of 2D WSe 2 pFET by Engineered Surface Charge Transfer Doping With Metal Co-Seeding
Surface charge transfer doping (SCTD) has emerged as a promising technique for doping 2D semiconductors, although it faces challenges in doping controllability, which impacts device performance. In this study, we introduce a novel approach to precisely control the p-type doping strength in solid-state SCTD for 2D WSe₂ field-effect transistors (FET) through metal co-seeding. By sequentially depositing molybdenum (Mo) and hafnium (Hf) metal seeds followed by O₂ annealing, we achieve improved doping control, while maintaining a high on/off current ratio. High-resolution transmission electron microscopy (HRTEM) images confirm the proposed co-seeding concept. This technique addresses doping controllability limitations in SCTD, enhances gate tunability, and it is viable for very-large-scale integration (VLSI) applications.
- Top Cited PapersOpen Access
- 19 July 2024
- Published by Springer Nature in npj Quantum Information
- Vol. 10 (1) , 1-9
Low charge noise quantum dots with industrial CMOS manufacturing
Silicon spin qubits are promising candidates for scalable quantum computers, due to their coherence and compatibility with CMOS technology. Advanced industrial processes ensure wafer-scale uniformity and high device yield, but traditional transistor processes cannot be directly transferred to qubit structures. To leverage the micro-electronics industry expertise, we customize a 300 mm wafer fabrication line for silicon MOS qubit integration. With careful optimization of the gate stack, we report uniform quantum dot operation at the Si/SiO2 interface at mK temperature. We measure a record-low average noise with a value of 0.61 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ at 1 Hz and even below 0.1 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ for some operating conditions. Statistical analysis of the charge noise measurements show that the noise source can be described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured spin qubits as a mature platform towards scalable high-fidelity qubits.- 19 July 2024
- Published by Springer Nature in npj Quantum Information
- Vol. 10 (1) , 1-9
Top Cited PapersOpen AccessLow charge noise quantum dots with industrial CMOS manufacturing
Silicon spin qubits are promising candidates for scalable quantum computers, due to their coherence and compatibility with CMOS technology. Advanced industrial processes ensure wafer-scale uniformity and high device yield, but traditional transistor processes cannot be directly transferred to qubit structures. To leverage the micro-electronics industry expertise, we customize a 300 mm wafer fabrication line for silicon MOS qubit integration. With careful optimization of the gate stack, we report uniform quantum dot operation at the Si/SiO2 interface at mK temperature. We measure a record-low average noise with a value of 0.61 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ at 1 Hz and even below 0.1 $${\rm{\mu }}{\rm{eVH}}{{\rm{z}}}^{-0.5}$$ for some operating conditions. Statistical analysis of the charge noise measurements show that the noise source can be described by a two-level fluctuator model. This reproducible low noise level, in combination with uniform operation of our quantum dots, marks CMOS manufactured spin qubits as a mature platform towards scalable high-fidelity qubits. - 25 September 2023
- Published by Springer Nature in Nature Electronics
- Vol. 6 (11) , 900-909
Multiplexed superconducting qubit control at millikelvin temperatures with a low-power cryo-CMOS multiplexer
- 25 September 2023
- Published by Springer Nature in Nature Electronics
- Vol. 6 (11) , 900-909
Multiplexed superconducting qubit control at millikelvin temperatures with a low-power cryo-CMOS multiplexer
- Open Access
Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.
Open AccessPhysics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low-temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2 K.
- 13 September 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nanotechnology
- Vol. 22 (1536125X) , 590-596
Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in bench-marking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2K
- 13 September 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nanotechnology
- Vol. 22 (1536125X) , 590-596
Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in bench-marking the benefits of cryogenic cooling for high-performance computing. In particular, the saturation of subthreshold swing due to band tails is an important phenomenon to include in low temperature analytical MOSFET models as it predicts theoretical lower bounds on the leakage power and supply voltage in tailored cryogenic CMOS technologies with tuned threshold voltages. Previous physics-based modeling required to evaluate functions with no closed-form solutions, defeating the purpose of fast and efficient model evaluation. Thus far, only the empirically proposed expressions are in closed form. This article bridges this gap by deriving a physics-based and closed-form model for the full saturating trend of the subthreshold swing from room down to low temperature. The proposed model is compared against experimental data taken on some long and short devices from a commercial 28-nm bulk CMOS technology down to 4.2K
- 13 July 2023
- Published by American Physical Society (APS) in Physical Review B
- Vol. 108 (4) , 045305
Modeling semiconductor spin qubits and their charge noise environment for quantum gate fidelity estimation
The spin of an electron confined in semiconductor quantum dots is currently a promising candidate for quantum bit (qubit) implementations. Taking advantage of the existing CMOS integration technologies, such devices can offer a platform for large scale quantum computation. However, a quantum mechanical framework bridging a device's physical design and operational parameters to the qubit's energy space is lacking. Furthermore, the spin to charge coupling introduced by intrinsic or induced spin-orbit interaction (SOI) exposes the qubits to charge noise compromising their coherence properties and inducing quantum gate errors. We present here a comodeling framework for double quantum dot (DQD) devices and their charge noise environments. We use a combination of an electrostatic potential solver, full configuration interaction quantum mechanical methods, and two-level-fluctuator models to study the quantum gate performance in realistic device designs and operation conditions. We utilize the developed models together alongside the single electron solutions of the quantum dots to simulate one- and two-qubit gates in the presence of charge noise. We find an inverse correlation between quantum gate errors and quantum dot confinement frequencies. We calculate X-gate fidelities in the simulated Si-MOS devices at a typical TLF density of . We also find that exchange driven two-qubit SWAP gates show higher sensitivity to charge noise with fidelities down to in the presence of the same density of TLFs. We further investigate the one- and two-qubit gate fidelities at different TLF densities. We find that given the small size of the quantum dots, sensitivity of a quantum gate to the distance between the noise sources and the quantum dot creates a strong variability in the quantum gate fidelities, which can compromise the device yields in scaled qubit technologies.- 13 July 2023
- Published by American Physical Society (APS) in Physical Review B
- Vol. 108 (4) , 045305
Modeling semiconductor spin qubits and their charge noise environment for quantum gate fidelity estimation
The spin of an electron confined in semiconductor quantum dots is currently a promising candidate for quantum bit (qubit) implementations. Taking advantage of the existing CMOS integration technologies, such devices can offer a platform for large scale quantum computation. However, a quantum mechanical framework bridging a device's physical design and operational parameters to the qubit's energy space is lacking. Furthermore, the spin to charge coupling introduced by intrinsic or induced spin-orbit interaction (SOI) exposes the qubits to charge noise compromising their coherence properties and inducing quantum gate errors. We present here a comodeling framework for double quantum dot (DQD) devices and their charge noise environments. We use a combination of an electrostatic potential solver, full configuration interaction quantum mechanical methods, and two-level-fluctuator models to study the quantum gate performance in realistic device designs and operation conditions. We utilize the developed models together alongside the single electron solutions of the quantum dots to simulate one- and two-qubit gates in the presence of charge noise. We find an inverse correlation between quantum gate errors and quantum dot confinement frequencies. We calculate X-gate fidelities in the simulated Si-MOS devices at a typical TLF density of . We also find that exchange driven two-qubit SWAP gates show higher sensitivity to charge noise with fidelities down to in the presence of the same density of TLFs. We further investigate the one- and two-qubit gate fidelities at different TLF densities. We find that given the small size of the quantum dots, sensitivity of a quantum gate to the distance between the noise sources and the quantum dot creates a strong variability in the quantum gate fidelities, which can compromise the device yields in scaled qubit technologies.- 12 June 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 230-231
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements
In this work, we report on the electrical performance of an ultra-low-power cryo-CMOS single-pole-4-throw (SP4T) RF multiplexer working at 10 mK base temperature stage of a dilution refrigerator. We use the multiplexer to benchmark a superconducting qubit for the very first time and obtain qubit coherence times of over 35 μs along with an average single-qubit gate fidelity of 99.93%, which exceeds the threshold required for quantum error-correction based on surface-code. This work demonstrates the operability of superconducting qubits with ultra-low-power cryo-CMOS devices at the base temperature, paving the way for advanced co-integration schemes.
- 12 June 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 230-231
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements
In this work, we report on the electrical performance of an ultra-low-power cryo-CMOS single-pole-4-throw (SP4T) RF multiplexer working at 10 mK base temperature stage of a dilution refrigerator. We use the multiplexer to benchmark a superconducting qubit for the very first time and obtain qubit coherence times of over 35 μs along with an average single-qubit gate fidelity of 99.93%, which exceeds the threshold required for quantum error-correction based on surface-code. This work demonstrates the operability of superconducting qubits with ultra-low-power cryo-CMOS devices at the base temperature, paving the way for advanced co-integration schemes.
- 3 May 2022
- Published by Elsevier in Thin Solid Films
- Vol. 753
A combinatorial study of SiGeAsTe thin films for application as an Ovonic threshold switch selector
- 3 May 2022
- Published by Elsevier in Thin Solid Films
- Vol. 753
A combinatorial study of SiGeAsTe thin films for application as an Ovonic threshold switch selector