Cong Wang

Analog computing has gained increasing attention for its potential in artificial intelligence hardware. The computation in traditional analog systems relies on use of intrinsic physical quantities (e.g., resistance), which are prone to fluctuations due to environmental changes or repeated programming, leading to compromised precision. Here, we shift the reliance on intrinsic physical quantity of memory devices to geometric ratio of transistors, enabling ultrahigh-precision analog computation. We demonstrate an analog in-memory computing chip based on a standard complementary metal-oxide semiconductor process, achieving the highest precision reported to date. Enhanced by the proposed weight remapping technique, the chip realizes ultrahigh computing accuracy with a root mean square error of only 0.101% across multiple parallel vector-by-matrix multiplication operations. Moreover, our analog in-memory computing chip maintains high precision, with an error of 0.155 and 0.130% under environmental temperatures of −78.5° and 180°C, respectively. This work pushes the boundaries of analog computing precision by leveraging stable geometry feature of devices.

In-memory computing hardware based on memristors has emerged as a promising option for scientific computing due to its large-scale parallel data processing capability. However, the nonuniformity issue of the memristors renders the practical deployment of in-memory computing hardware complex, requiring peripheral circuits to ensure the accuracy of scientific computing, thereby resulting in increased power consumption. Here, we present a mortise-tenon–shaped (MTS) memristor with ultrahigh uniformity by introducing a mortise-shaped h-BN flake on the HfO ₂ switching layer. The MTS memristor exhibits ultrasmall cycle-to-cycle (~2.5%) and device-to-device (~6.9%) variations compared to the HfO ₂ memristor without the MTS structure. Furthermore, we use the MTS memristors to build a partial differential equation solver and demonstrate a convergence speed of solving the Poisson equation five times faster than the solver based on the traditional HfO ₂ memristors. This work provides a promising approach for notably reducing the hardware resources required for fast and high-accuracy scientific computing.

The development of complementary metal-oxide-semiconductor field-effect transistor (CMOSFET) based on two-dimensional (2D) materials offers an important opportunity to reduce static power and increase the integration density of integrated circuits. One promising approach to realize these CMOSFETs is to employ ambipolar 2D materials as channel materials with designed device structure to control the carrier transport properties for CMOSFET characteristics. However, these devices always suffer from complex multi-gate electrode structure, and hence face challenges in complicated inter-connection design and excessive voltage source requirement for circuit implementation. Here, we develop a three-terminal CMOSFET using ambipolar 2D material based on the drain electric field-induced carrier injection self-blocking mechanism. The designed drain electrode can effectively suppress carrier injection from the drain to the channel material, while the gate voltage can only regulate carrier injection in the source region. As a result, we can configure the device as either N-field-effect transistors (FET) or P-FET with a high current on/off ratio of over 105 by adjusting the three voltages (gate, source, and drain). Furthermore, we utilize these devices to demonstrate multifunctional wave modulator, low-static-power logic inverter (<5 pW), and combinational logic computing in the form of a compact complementary circuit. Our work would explore an efficient approach for implementing complementary circuits using 2D materials.

Memristor crossbar arrays are expected to achieve highly energy-efficient neuromorphic computing via implementing parallel vector–matrix multiplication (VMM) in situ. The similarities between memristors and neural synapses offer opportunities for realizing hardware-based brain-inspired computing, such as spike neural networks. However, the nonlinear I–V characteristics of the memristors limit the implementation of parallel VMM on passive memristor crossbar arrays. In our work, we propose to utilize differential conductance as a synaptic weight to implement linear VMM operations on a passive memristor array in parallel. We fabricated a TiO2/HfO2 memristor crossbar array, in which differential-conductance-based synaptic weight exhibits plasticity, nonvolatility, multi-states, and tunable ON/OFF ratio. The noise-dependent accuracy performance of VMM operations based on the proposed approach was evaluated, offering an optimization guideline. Furthermore, we demonstrated a spike neural network circuit capable of processing small spiking signals through the differential-conductance-based synapses. The experimental results showcase effective space-coded and time-coded spike pattern recognition. Importantly, our work opens up new possibilities for the development of passive memristor arrays, leading to increased energy and area efficiency in brain-inspired chips.