Yimin Gao

This paper presents a Virtualized Computational Radio Frequency Identification (VCRFID) solution that utilizes far-field UHF RF for sensing, computing, and self-powering at the edge. A standard UHF RFID system is asymmetric as it consists of a relatively large, complex “reader”, which acts as an RF transmitter and controller for a number of small simple battery-less “tags”, which work in passive mode as they communicate and harvest RF energy from the reader. Previously proposed Computational RFID (CRFID) solutions enhance the standard RFID tags with microcontrollers and sensors in order to gain enhanced functionality, but they end up requiring a relatively high level of power, and thus ultimately reduced range, which limits their use for many Internet-of-Things (IoT) application scenarios. Our VCRFID solution instead keeps the functionality of the tags minimalistic by only providing a sensor interface to be able to capture desired environmental data (temperature, humidity, vibration, etc.), and then transmit it to the RFID reader, which then performs all the computational load usually carried out by a microcontroller on the tag in prior work. This virtualization of functions enables the design of a circuit without a microcontroller, providing greater flexibility and allowing for wireless reconfiguration of tag functions over RF for a 97% reduction in energy consumption compared to prior energy-harvesting RFID tags with microcontrollers. The target application is Industry 4.0 where our VCRFID solution enables battery-less fine-grain monitoring of vibration and temperature data for pumps and motors for predictive maintenance scenarios.

In-memory database query processing frequently involves substantial data transfers between the CPU and memory, leading to inefficiencies due to Von Neumann bottleneck. Processing-in-Memory (PIM) architectures offer a viable solution to alleviate this bottleneck. In our study, we employ a commonly used software approach that streamlines JOIN operations into simpler selection or filtering tasks using pre-join denormalization which makes query processing workload more amenable to PIM acceleration. This research explores DRAM design landscape to evaluate how effectively these filtering tasks can be efficiently executed across DRAM hierarchy and their effect on overall application speedup. We also find that operations such as aggregates are more suitably executed on the CPU rather than PIM. Thus, we propose a cooperative query processing framework that capitalizes on both CPU and PIM strengths, where (i) the DRAM-based PIM block, with its massive parallelism, supports scan operations while (ii) CPU, with its flexible architecture, supports the rest of query execution. This allows us to utilize both PIM and CPU where appropriate and prevent dramatic changes to the overall system architecture. With these minimal modifications, our methodology enables us to faithfully perform end-to-end performance evaluations using established analytics benchmarks such as TPCH and star-schema benchmark (SSB). Our findings show that this novel mapping approach improves performance, delivering a 5.92x/6.5x speedup compared to a traditional schema and 3.03-4.05x speedup compared to a denormalized schema with 9-17% memory overhead, depending on the degree of partial denormalization. Further, we provide insights into query selectivity, memory overheads, and software optimizations in the context of PIM-based filtering, which better explain the behavior and performance of these systems across the benchmarks.

Layer-wise mixed-precision quantization (MPQ) has become prevailing for edge inference since it strikes a better balance between accuracy and efficiency compared to the uniform quantization scheme. Existing MPQ strategies either lacked hardware awareness or incurred huge computation costs, which gated their deployment at the edge. In this work, we propose a novel MPQ search algorithm that obtains an optimal scheme by "sampling" layer-wise sensitivity with respect to a newly proposed metric that incorporates both accuracy and proxy of hardware cost. To further efficiently deploy post-training MPQ on edge chips, we propose to tightly integrate the quantized inference units as part of the processor pipeline through micro-architecture and Instruction Set Architecture (ISA) co-design. Evaluation results show that the proposed search algorithm achieves 3% ~ 11% higher inference accuracy with similar hardware cost compared to the state-of-the-art MPQ strategies. In addition, the tightly integrated MPQ units achieve speedup of 15.13x ~ 29.65x compared to a baseline RISC-V processor.