Danny Wan

We demonstrate high-fidelity single qubit control in a natural Si-MOS quantum dot fabricated in an industrial 300 mm wafer process on a silicon on insulator wafer using electron spin resonance. A relatively high optimal Rabi frequency of 5 MHz is achieved, decoupling the electron spin from its 29Si environment. Tracking the qubit frequency reduces the impact of low-frequency noise in the qubit frequency and improves the TRabi from 7 to 11 μs at a Rabi frequency of 5 MHz, resulting in Q-factors exceeding 50. Randomized benchmarking returns an average single gate control fidelity of 99.5±0.3%. As a result of pulse-area calibration, this fidelity is limited by the Rabi Q-factor. These results show that a fast Rabi frequency and a feedback protocol enable high fidelity in these Si-MOS devices, despite the low-frequency magnetic noise.

We introduce a multimode superconducting inductor architecture that enables radio frequency reflectometry at multiple discrete frequencies up to 2 GHz, addressing limitations of conventional single-mode designs. The spiral inductor's distributed capacitance yields distinct resonant modes with varied impedance-matching conditions. By probing a quantum dot across several modes, we extract tunneling rates over a broad frequency range and identify signatures of nearby charge defects. Using a higher-order mode of the distributed inductor, rather than the fundamental mode, we demonstrate single-shot spin readout via a radio frequency single-electron transistor (RF-SET), achieving singlet-triplet readout with an integration time of 8 μs and a readout fidelity of 98%. These results establish multimode inductance as a scalable and flexible component for fast spin qubit readout and device-quality characterization.

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the FPGA embedded in Keysight's Quantum Engineering Toolkit (QET), the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

Testing of spin-based quantum devices is currently performed through quantum dot and qubit measurements at deep cryogenic temperatures, well below 1 K. At such low temperatures, the testing throughput is strongly limited due to the long cool-down times and due to the large number of connections required between the device at deep-cryogenic temperature and the room-temperature control electronics. As the number of qubits in a single chip increases and as we advance toward large-scale manufacturing, developing effective techniques that allow to screen those chips at higher temperatures, possibly even room temperature, becomes indispensable. Transistor metrics constitute a promising indicator to identify, at room temperature, which devices are functional and also at cryogenic temperatures. Prior work has demonstrated a strong correlation between quantum dot metrics measured at deep-cryogenic temperature and transistor metrics up to 77 K. To ensure that such a correlation extends up to room temperature, electrostatic confinement of the conductive channel needs to be guaranteed. In this article, we propose a single-electron transistor (SET) design intended for the correlation study of transistor metrics from deep-cryogenic up to room temperatures. Our calibrated technology computer-aided design (TCAD) simulation results demonstrate the drastic improvement of the room-temperature transistor behavior of the proposed design, without the employment of physical device isolation that would negatively impact the qubit’s fidelity. In addition, this work presents a room-temperature-aware methodology in the design phase of spin-based devices, with promising scalability to structures containing a larger number of qubits.

Electron-spin qubits are among the most promising platforms for the realization of a large-scale quantum computer. Physical limitations dictate their operation at cryogenic temperatures, in practice often well below 1 K. This requirement implies the employment of a refrigerator featuring long cooldown times and the need for die packaging, thereby strongly limiting the number of devices that can be measured simultaneously. In our work, we evaluate traditional transistor metrics to enable fast wafer-level screening of electron-spin qubit devices above cryogenic temperatures. To the best of our knowledge, a clear link between quantum dot metrics measured below 2 K and traditional transistor metrics measured at higher temperatures has not yet been identified. In this letter, we study the correlation between 10 mK measurements in the few-electron regime, and traditional transistor metrics at different temperatures. We observe a strong correlation up to 77 K, while correlations at higher temperatures are much less pronounced. We analyze this poor correlation via room-temperature TCAD simulations, showing that the underlying physics changes due to a considerable contribution of the substrate current to the device’s off current above 77 K.

In this work, we report on the electrical performance of an ultra-low-power cryo-CMOS single-pole-4-throw (SP4T) RF multiplexer working at 10 mK base temperature stage of a dilution refrigerator. We use the multiplexer to benchmark a superconducting qubit for the very first time and obtain qubit coherence times of over 35 μs along with an average single-qubit gate fidelity of 99.93%, which exceeds the threshold required for quantum error-correction based on surface-code. This work demonstrates the operability of superconducting qubits with ultra-low-power cryo-CMOS devices at the base temperature, paving the way for advanced co-integration schemes.