Kristiaan De Greve

Silicon spin qubits in gate-defined quantum dots leverage established semiconductor infrastructure and offer a scalable path toward transformative quantum technologies. Holes spins in silicon offer compact all-electrical control, whilst retaining the salient features of a quantum dot qubit architecture. However, silicon hole spin qubits are not as advanced as electrons, due to increased susceptibility to disorder and more complex spin physics. Here we demonstrate single-qubit gate fidelities up to 99.8% and a two-qubit gate quality factor of 240, indicating a physical fidelity limit of 99.7%. These results represent the highest performance reported in natural silicon to date, made possible by fast qubit control, exchange pulsing, and industrial-grade fabrication. Notably, we achieve these results in a near-identical device as used for highly reproducible, high-fidelity electron spin qubits. With isotopic purification and further device-level optimisations, silicon hole spin qubits are poised to unlock a new operation regime for quantum CMOS architectures.

The 22nm fully-depleted silicon-on-insulator (FDSOI) technology is considered near-ideal for creating low-power cryogenic control electronics, a key milestone in the pursuit of large-scale fault-tolerant quantum computers. However, it is essential to assess the device reliability under conditions of interest, as various gate stack reliability phenomena such as bias temperature instability (BTI) and hot carrier degradation (HCD) have been reported active at 4K. This study comprehensively analyzes the shift in device parameters induced by BTI stress and recovery from room temperature down to 4K. A new method of assessing the impact of cryogenic BTI on ultra-low-power applications is presented, showcasing how nMOS devices of the 22nm technology prove to be ready for long-term cryo-operation, whereas pMOS devices do not.

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the FPGA embedded in Keysight's Quantum Engineering Toolkit (QET), the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

Materials that feature very high permittivity and very low losses at low temperatures offer interesting opportunities for improving the performance of a variety of microwave-optical devices such as phase shifters and quantum transducers. In this Letter, superconducting Al coplanar waveguide resonators between 4 and 6 GHz were used to determine the complex permittivity and loss of thin film SrTiO3 on Si at cryogenic temperatures. We report a permittivity of 1950 ± 140 and a high-power loss tangent (tan δSTO) of 3.4 ± 0.1×10−4 at millikelvin temperatures. To further investigate the potential of SrTiO3 for use in emerging quantum technology applications, the transition of tan δSTO into the single photon regime was analyzed. Our findings reveal a loss scaling that aligns closely with a two-level system loss mechanism. We observe a nearly two orders of magnitude difference in tan δSTO between high and low input power levels, consistent with that two-level system loss picture.

Pockels materials are notable for their strong electro-optic interaction and rapid response times and are therefore used extensively in optical communications. However, at cryogenic temperatures, Pockels coefficients are reduced in many materials optimized for room-temperature operation, which is a major hurdle for emerging quantum technologies. Here, we show that strontium titanate (SrTiO ₃ ) can be engineered to exhibit a Pockels coefficient of 345 picometers per volt at 20 hertz at cryogenic temperatures, a value twice as high as any other thin-film electro-optic material. By adjusting the stoichiometry, we were able to increase the Curie temperature and realize a ferroelectric phase yielding a high Pockels coefficient, so far with limited optical losses of decibels per centimeter. Our findings position SrTiO ₃ as a promising material for cryogenic quantum photonics applications.

The realization of practical, large-scale quantum computers requires the optimization of classical electronics for cryogenic operation to solve the interconnect bottleneck between quantum processors and control electronics. Devices from Fully-depleted Silicon-on-insulator (FDSOI) technology nodes are ideal for cryogenic operation due to the possibility of tuning the threshold voltage through the back-gate and reducing power consumption. However, they must be assessed in terms of not just their performance but also their reliability at conditions of interest. In this study, we present the Bias Temperature Instability (BTI) characteristics of commercial 22 nm FDSOI transistors optimized for low-power applications at temperatures ranging from 300 K down to 4 K, focusing on the impact of stress time and gate overdrive voltage. We observe that BTI remains active in both pMOS and nMOS at 4K with weak dependencies on stress magnitude and duration. Crucially, recovery from threshold voltage shifts is also slowed down at cryogenic temperatures.