Alexandre Siligaris
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Alexandre Siligaris has a total of 41 co-authors. Here are the top co-authors by number of shared publications:
- José Luis González
Université Grenoble-Alpes, CEA-Leti, Minatec Campus, Grenoble, France
5 shared publications - Antonio Clemente
Université Grenoble Alpes CEA‐LETI Grenoble France
2 shared publications - Clement Jany
French Alternative Energies and Atomic Energy Commission (CEA), Grenoble, France
2 shared publications - Cédric Dehos
Univ. Grenoble Alpes, CEA, LETI, Grenoble, France
2 shared publications - Francesco Foglia Manzillo
Univ. Grenoble Alpes, CEA, LETI
2 shared publications - Nicolas Cassiau
Univ. Grenoble Alpes, CEA, LETI, Grenoble, France
2 shared publications
Latest Publications
- 20 May 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Microwave and Wireless Technology Letters
- Vol. 34 (6) , 801-804
An Energy-Efficient 56-Gb/s D-Band TX-to-RX Link Using CMOS ICs and Transmitarray Antennas
This letter presents an energy-efficient system with a transmitter and a receiver comprising multichannel integrated circuits (ICs) in 45-nm CMOS technology and antennas-in-package feeding high-directivity planar lenses. Data rates up to 56 Gb/s are demonstrated over a 1-m point-to-point link using a full-digital communication system. The active circuits integrate multiple local oscillator generators for implementing a channel-aggregation architecture that provides a large radio frequency (RF) bandwidth (BW) using a significantly narrower baseband (BB) interface BW. The energy consumption of the overall system is only 33 pJ/bit.
- 20 May 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Microwave and Wireless Technology Letters
- Vol. 34 (6) , 801-804
An Energy-Efficient 56-Gb/s D-Band TX-to-RX Link Using CMOS ICs and Transmitarray Antennas
This letter presents an energy-efficient system with a transmitter and a receiver comprising multichannel integrated circuits (ICs) in 45-nm CMOS technology and antennas-in-package feeding high-directivity planar lenses. Data rates up to 56 Gb/s are demonstrated over a 1-m point-to-point link using a full-digital communication system. The active circuits integrate multiple local oscillator generators for implementing a channel-aggregation architecture that provides a large radio frequency (RF) bandwidth (BW) using a significantly narrower baseband (BB) interface BW. The energy consumption of the overall system is only 33 pJ/bit.
- 24 October 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 72 (1) , 836-850
A D-Band Transmitter Achieving 57.6-Gb/s and 30-dBm EIRP Based on Channel-Aggregation 45-Nm ICs and a Low-Profile Flat Lens Antenna
We present two high-efficiency baseband (BB)-to- D -Band transmitting systems based on a novel channel-aggregation architecture. They comprise a first integrated circuit (IC) for channel aggregation at intermediate frequency (IF) and a two-channel 45-nm CMOS transmitter (TX) flip-chipped on antenna-in-package (AiP), which illuminates a high-gain flat lens antenna in standard printed circuit board technology. The two signals emitted by the active antenna module, in adjacent bands, are aggregated over the air and collimated by the flat lens. Two TXs using a standard and a folded transmitarray antenna (TA), three times thinner than the former one, are realized and compared. They achieve similar performance in the operating band (139.3–156.6 GHz), with a measured peak effective isotropic radiated power (EIRP) of 30 dBm. A wireless point-to-point link is demonstrated with the proposed transmitting system and a commercial receiver. A data rate (DR) of 57.6 Gb/s is measured at 1 m using eight channels and a 16-quadrature amplitude modulation (QAM) scheme, with an energy efficiency of 27.4 pJ/b.
- 24 October 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 72 (1) , 836-850
A D-Band Transmitter Achieving 57.6-Gb/s and 30-dBm EIRP Based on Channel-Aggregation 45-Nm ICs and a Low-Profile Flat Lens Antenna
We present two high-efficiency baseband (BB)-to- D -Band transmitting systems based on a novel channel-aggregation architecture. They comprise a first integrated circuit (IC) for channel aggregation at intermediate frequency (IF) and a two-channel 45-nm CMOS transmitter (TX) flip-chipped on antenna-in-package (AiP), which illuminates a high-gain flat lens antenna in standard printed circuit board technology. The two signals emitted by the active antenna module, in adjacent bands, are aggregated over the air and collimated by the flat lens. Two TXs using a standard and a folded transmitarray antenna (TA), three times thinner than the former one, are realized and compared. They achieve similar performance in the operating band (139.3–156.6 GHz), with a measured peak effective isotropic radiated power (EIRP) of 30 dBm. A wireless point-to-point link is demonstrated with the proposed transmitting system and a commercial receiver. A data rate (DR) of 57.6 Gb/s is measured at 1 m using eight channels and a 16-quadrature amplitude modulation (QAM) scheme, with an energy efficiency of 27.4 pJ/b.
- 13 June 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
A High-Order-N Frequency-Multiplier Using Pulsed Oscillator: Modeling and Optimization
This work focusses on the modeling of the Phase Noise (PhN) through the building blocks of a high-order-N frequency multiplication circuit that uses Pulsed injection Locking Oscillator (P-OSC). The proposed analytical expressions allow predicting the transformation of PhN through different blocks of the frequency multiplier. To cope with the inherent nonlinear characteristics of frequency multiplication circuits, simplified nonlinear equivalent circuits (NEC) are used to loosen the time and memory constraints of the numerical simulations. The analytical results show good agreements with Harmonic Balance simulations of NEC. This work helps determining the circuit key parameters controlling Phase Noise and output integrated RMS Jitter for optimization purposes.
- 13 June 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
A High-Order-N Frequency-Multiplier Using Pulsed Oscillator: Modeling and Optimization
This work focusses on the modeling of the Phase Noise (PhN) through the building blocks of a high-order-N frequency multiplication circuit that uses Pulsed injection Locking Oscillator (P-OSC). The proposed analytical expressions allow predicting the transformation of PhN through different blocks of the frequency multiplier. To cope with the inherent nonlinear characteristics of frequency multiplication circuits, simplified nonlinear equivalent circuits (NEC) are used to loosen the time and memory constraints of the numerical simulations. The analytical results show good agreements with Harmonic Balance simulations of NEC. This work helps determining the circuit key parameters controlling Phase Noise and output integrated RMS Jitter for optimization purposes.
- Open Access
- 2 February 2021
- Published by Sissa Medialab Srl
- Vol. 390, 832
Wireless Allowing Data and Power Transfer
The WADAPT consortium (Wireless Allowing Data and Power Transfer) was created to study wireless (multi-gigabit) data transfer for high-energy physics applications (LoI, CERN-LHCC-2017-002; LHCC-I-028.-2017). Emerging millimetre wave technologies allow fast signal transfer and efficient partitioning of detectors in topological regions of interest. Large bandwidths are available at those frequencies, allowing very high data rates at short range and conveniently substituting a mass of materials (cables and connectors). The Wadapt initiative aims at building proof of concept for use in future HEP experiments. For vertex detectors at HL-LHC, the bandwidth of 60 GHz is adequate and commercial products are already available, providing 6 Gbps data links. Products have been tested for signal confinement, crosstalk, electromagnetic immunity and resistance to radiation. An HEP dedicated 60 GHz Integrated Chip is being built in Heidelberg, using 130 nm SiGe BICMOS technology. It should assess the feasibility and performance of the wireless link and establish solid foundation for designing the final reading system. At longer terms, 140 GHz bands could also be used for higher data rates (> 100 Gbps) for future FCC applications. Wireless reading could widespread to many detectors, with the possibility of adding intelligence on the detector to perform four-dimensional reconstruction of the traces and vertexes online, in order to attach the traces to their vertex with great efficiency even in difficult experimental conditions. The WADAPT project includes also a long-term step aimed at transmitting energy wirelessly. This would create a new paradigm for the transmission of data and power in particle physics detectors.
- 2 February 2021
- Published by Sissa Medialab Srl
- Vol. 390, 832
Open AccessWireless Allowing Data and Power Transfer
The WADAPT consortium (Wireless Allowing Data and Power Transfer) was created to study wireless (multi-gigabit) data transfer for high-energy physics applications (LoI, CERN-LHCC-2017-002; LHCC-I-028.-2017). Emerging millimetre wave technologies allow fast signal transfer and efficient partitioning of detectors in topological regions of interest. Large bandwidths are available at those frequencies, allowing very high data rates at short range and conveniently substituting a mass of materials (cables and connectors). The Wadapt initiative aims at building proof of concept for use in future HEP experiments. For vertex detectors at HL-LHC, the bandwidth of 60 GHz is adequate and commercial products are already available, providing 6 Gbps data links. Products have been tested for signal confinement, crosstalk, electromagnetic immunity and resistance to radiation. An HEP dedicated 60 GHz Integrated Chip is being built in Heidelberg, using 130 nm SiGe BICMOS technology. It should assess the feasibility and performance of the wireless link and establish solid foundation for designing the final reading system. At longer terms, 140 GHz bands could also be used for higher data rates (> 100 Gbps) for future FCC applications. Wireless reading could widespread to many detectors, with the possibility of adding intelligence on the detector to perform four-dimensional reconstruction of the traces and vertexes online, in order to attach the traces to their vertex with great efficiency even in difficult experimental conditions. The WADAPT project includes also a long-term step aimed at transmitting energy wirelessly. This would create a new paradigm for the transmission of data and power in particle physics detectors.
- 1 September 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 314-317
A D-band 4-ways power splitter/combiner implemented on a 28nm bulk CMOS process
- 1 September 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 314-317
A D-band 4-ways power splitter/combiner implemented on a 28nm bulk CMOS process
- 1 October 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1413-1416
A 30–50 GHz reflection-type phase shifter based on slow-wave coupled lines in BiCMOS 55 nm technology
This paper presents a mm-wave compact, ultra-wideband reflection-type phase shifter (RTPS). This phase shifter is dedicated to phased array transmitter based on LO-path phase shifting for beamforming and beam-steering applications in the sub-mm-wave band. The proposed RTPS is designed using a slow-wave coplanar waveguide coupler and reflective loads. The circuit was fabricated in BiCMOS 55 nm technology. As predicted by simulations, measurement results show a relative phase shift of 61°±1° that is very stable over a wide frequency range from 30 GHz to 50 GHz, with insertion loss of 4 dB ± 1 dB at 50 GHz, leading to a figure-of-merit (FoM) of 12°/dB. The measured return loss is always better than 10 dB across the whole band. The chip area is only 0.18 mm 2 .
- 1 October 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1413-1416
A 30–50 GHz reflection-type phase shifter based on slow-wave coupled lines in BiCMOS 55 nm technology
This paper presents a mm-wave compact, ultra-wideband reflection-type phase shifter (RTPS). This phase shifter is dedicated to phased array transmitter based on LO-path phase shifting for beamforming and beam-steering applications in the sub-mm-wave band. The proposed RTPS is designed using a slow-wave coplanar waveguide coupler and reflective loads. The circuit was fabricated in BiCMOS 55 nm technology. As predicted by simulations, measurement results show a relative phase shift of 61°±1° that is very stable over a wide frequency range from 30 GHz to 50 GHz, with insertion loss of 4 dB ± 1 dB at 50 GHz, leading to a figure-of-merit (FoM) of 12°/dB. The measured return loss is always better than 10 dB across the whole band. The chip area is only 0.18 mm 2 .
- 1 October 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 22, 1020-1023
A novel programmable harmonic selection technique based on the pseudo-locking of an oscillator by periodically repeated oscillations train
A new concept based on the injection of a periodically repeated oscillations train into an oscillator is presented. It is based on a phenomenon named pseudo-locking, leading to a novel programmable harmonic selection technique. Theoretical description of the concept is presented, in particular an analytical condition is carried out, paving the way of design rules. For a proof of concept, an oscillator fabricated on a 40 nm CMOS technology was measured. The concept was validated by measured phase noise equivalent to classical fundamental injection locking phase noise performance.
- 1 October 2014
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 22, 1020-1023
A novel programmable harmonic selection technique based on the pseudo-locking of an oscillator by periodically repeated oscillations train
A new concept based on the injection of a periodically repeated oscillations train into an oscillator is presented. It is based on a phenomenon named pseudo-locking, leading to a novel programmable harmonic selection technique. Theoretical description of the concept is presented, in particular an analytical condition is carried out, paving the way of design rules. For a proof of concept, an oscillator fabricated on a 40 nm CMOS technology was measured. The concept was validated by measured phase noise equivalent to classical fundamental injection locking phase noise performance.